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| MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 3807 group is a 8-bit microcomputer based on the 740 family core technology. The 3807 group has two serial I/Os, an A-D converter, a D-A converter, a real time output port function, a watchdog timer, and an analog comparator, which are available for a system controller which controls motors of office equipment and household appliances. The various microcomputers in the 3807 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3807 group, refer to the section on group expansion. * * * * * * * * FEATURES * * * * * * * * * * Basic machine-language instructions ....................................... 71 The minimum instruction execution time ............................ 0.5 s (at 8 MHz oscillation frequency) Memory size ................................................................................. ROM ................................................ 8 to 60 K bytes RAM ............................................ 384 to 2048 bytes Programmable input/output ports ............................................. 68 Software pull-up resistors (Ports P0 to P2) .............................. 24 Input ports (Ports P63 and P64) ................................................. 2 Interrupts .................................................. 20 sources, 16 vectors Timers X, Y .................................................................. 16-bit ! 2 Timers A, B (for real time output port function) ............ 16-bit ! 2 Timers 1-3 ..................................................................... 8-bit ! 3 * * * Serial I/O1 (UART or Clock-synchronized) .................... 8-bit ! 1 Serial I/O2 (Clock-synchronized) ................................... 8-bit ! 1 A-D converter ................................................ 8-bit ! 13 channels D-A converter .................................................. 8-bit ! 4 channels Watchdog timer ............................................................ 16-bit ! 1 Analog comparator ........................................................ 1 channel 2 Clock generating circuit Main clock (XIN-XOUT) .......................... Internal feedback resistor Sub-clock (XCIN-XCOUT) .......... Without internal feedback resistor (connect to external ceramic resonator or quartz-crystal oscillator) Power source voltage In high-speed mode ................................................... 4.0 to 5.5 V (at 8 MHz oscillation frequency and high-speed selected) In middle-speed mode ................................................ 2.7 to 5.5 V (at 8 MHz oscillation frequency and middle-speed selected) In low-speed mode ..................................................... 2.7 to 5.5 V (at 32 kHz oscillation frequency and low-speed selected) Power dissipation In high-speed mode ......................................................... 34 m W (at 8 MHz oscillation frequency, at 5 V power source voltage) In low-speed mode ............................................................. 60 W (at 32 kHz oscillation frequency, at 3 V power source voltage) Memory expansion .......................................................... possible Operating temperature range ................................... -20 to 85 C APPLICATION LBP engine control, PPC, FAX, office equipment, household appliances, consumer electronics, etc. PIN CONFIGURATION (TOP VIEW) P30/RTP6 P31/RTP7 P32/ONW P33/RESETOUT P34/CKOUT/ P35/SYNC P36/WR P37/RD P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P15/AD13 P16/AD14 P17/AD15 55 60 59 61 56 57 58 62 63 64 53 52 51 50 49 48 47 46 45 44 43 42 P87/RTP5 P86/RTP4 P85/RTP3 P84/RTP2 P83/RTP1 P82/RTP0 P81/DA4/AN12 P80/DA3/AN11 VCC ADVREF AVSS P65/DAVREF/AN10 P64/CMPREF /AN9 P63/CMPIN /AN8 CMPOUT CMPVCC 54 41 40 39 38 37 36 35 34 33 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 M38073M4-XXXFP 32 31 30 29 28 27 26 25 P20/DB0 P21/DB1 P22/DB2 P23/DB3 P24/DB4 P25/DB5 P26/DB6 P27/DB7 VSS XOUT XIN P40/XCOUT P41/XCIN RESET CNVSS P42/INT0 11 12 13 14 15 16 17 18 19 20 Fig. 1. Pin configuration of M38073M4-XXXFP P62/AN7 P61/AN6 P60/AN5 P77/AN4 P76/AN3 P75/AN2 P74/AN1 P73/SRDY2/ADT/AN0 P72/SCLK2 P71/SOUT2 P70/SIN2 P57/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/INT4 P52/INT3 P51/SCMP2/INT2 P50/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 Package type : 80P6N-A 80-pin plastic-molded QFP 10 21 22 23 24 1 2 3 4 5 6 7 8 9 2 Reset input V SS CC 27 26 73 32 FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N) Main clock Main clock input output V RESET CNVSS X IN X OUT 30 31 FUNCTIONAL BLOCK Sub-clock Sub-clock output input Fig. 2. Functional block diagram CPU XCIN XCOUT Clock generating circuit RAM ROM X Timer 1 (8) Timer X (16) S CNTR0 INT0 CNTR1 INT1 A Timer 3 (8) Timer 2 (8) TOUT CMPVCC 80 Y CMPIN CMPOUT 79 Analog comparator PS PC H PCL Timer Y (16) CMPREF Timer A (16) Timer B (16) D-A D-A SI/O2(8) SCMP2 (8) D-A converter 2 (8) D-A converter 1 (8) A-D converter SI/O1(8) RTP converter 4 converter 3 RTP0 - INT2 - INT4 (8) (8) RTP5 SCMP2 INT0, XCIN INT1 XCOUT RTP0 - INT4 RTP5 P8(8) TOUT CMPREF DAVREF CMPIN P7(8) P6(8) P5(8) P4(8) P3(8) P2(8) P1(8) P0(8) 65 66 67 68 69 70 71 72 4 5 6 7 8 9 10 11 76 77 78 123 74 75 12 13 14 15 16 17 18 19 20 21 22 23 24 25 28 29 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O port P 8 I/O port P 6 I/O port P 7 I/O port P 5 I/O port P 4 I/O port P 3 I/O port P 2 I/O port P 1 I/O port P 0 ADVREF AVSS MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Table. 1. Pin description (1) Pin VCC, VSS CMPVCC CNVSS Name Function Function except a port function Power source * Apply voltage of 2.7-5.5 V to VCC, and 0 V to VSS. Analog comparator * Power source input pin for an analog comparator power source CNVSS * This pin controls the operation mode of the chip. * Normally connected to VSS. Analog reference voltage Analog power source * If this pin is connected to VCC, the internal ROM is inhibited and external memory is accessed. * Reference voltage input pin for A-D converter. * Analog power source input pin for A-D and D-A converter and an analog comparator * Connect to VSS. ADVREF AVSS CMPOUT ______ RESET XIN XOUT P00-P07 P10-P17 P20-P27 Analog comparator * Output pin for an analog comparator output Reset input * Reset input pin for active "L" Clock input * Input and output signals for the internal clock generating circuit. * Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. Clock output I/O port P0 I/O port P1 I/O port P2 * If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open. * The clock is used as the oscillating source of system clock. * 8-bit CMOS I/O port * I/O direction register allows each pin to be individually programmed as either input or output. * At reset this port is set to input mode. * In modes other than single-chip, these pins are used as address, data bus I/O pins. * CMOS compatible input level * CMOS 3-state output structure * Port P2 can be switched CMOS or TTL input level. P30/RTP6, P31/RTP7 P34/CKOUT, P32, P33, P35-P37 I/O port P3 * 8-bit CMOS I/O port * I/O direction register allows each pin to be individually programmed as either input or output. * Real time port function pins * At reset this port is set to input mode. * Clock output function pin * In modes other than single-chip, these pins are used as control bus I/O pins. * CMOS compatible input level * CMOS 3-state output structure * Port P32 can be switched CMOS or TTL input level. * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures * Sub-clock generating I/O pins(connect a resonator) * Interrupt input pins * Timer X, Timer Y function pins (INT0, INT1) * Serial I/O1 function pins P40/XCOUT, I/O port P4 P41/XCIN P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/TOUT P51/SCMP2/ INT2 P52/INT3, P53/INT4 P54/CNTR0, P55/CNTR1 P56/DA1, P57/DA2 I/O port P5 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * Timer 2 output pin * Interrupt input pin * Serial I/O2 function pin * Interrupt input pin * Real time port function pin(INT4) * Timer X, Timer Y function pins * D-A conversion output pins 3 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 2. Pin description (2) Pin P60/AN5- P62/AN7 Name I/O port P6 Function * 3-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure P63/CMPIN/ Input port P6 AN8 P64/CMPREF/ AN9 P65/DAVREF/ I/O port P6 AN10 P70/SIN2, P71/SOUT2, P72/SCLK2 P73/SRDY2/ ADT/AN0 P74/AN1- P77/AN4 P80/DA3/ AN11, P81/DA4/ AN12, P82/RTP0- P87/RTP5 * Realtime port function pins I/O port P7 * 2-bit CMOS input port * CMOS compatible input level * Analog comparator input pin * A-D conversion input pin * Reference voltage input pin for analog comparator * A-D conversion input pin * D-A conversion power source input pin * A-D conversion input pin * Serial I/O2 function pins Function except a port function * A-D conversion output pins * 1-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structure * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures * Serial I/O2 function pin * A-D conversion input pin * A-D trigger input pin * A-D conversion input pin I/O port P8 * 8-bit CMOS I/O port with the same function as port P0 * CMOS compatible input level * CMOS 3-state output structures * D-A conversion output pin * A-D conversion input pin 4 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING Product M3807 3 M 4 - XXX FP Package type FP : 80P6N-A package FS : 80D0 package ROM number Omitted in some types. ROM/PROM size 1 : 4096 bytes 2 : 8192 bytes 3 : 12288 bytes 4 : 16384 bytes 5 : 20480 bytes 6 : 24576 bytes 7 : 28672 bytes 8 : 32768 bytes 9 : 36864 bytes A : 40960 bytes B : 45056 bytes C : 49152 bytes D : 53248 bytes E : 57344 bytes F : 61440 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M : Mask ROM version E : EPROM or One Time PROM version RAM size 0 : 192 bytes 1 : 256 bytes 2 : 384 bytes 3 : 512 bytes 4 : 640 bytes 5 : 768 bytes 6 : 896 bytes 7 : 1024 bytes 8 : 1536 bytes 9 : 2048 bytes Fig. 3. Part numbering 5 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3807 group as follows: Memory Type Support for Mask ROM, One Time PROM and EPROM versions. Memory Size ROM/PROM size .................................................... 8K to 60K bytes RAM size ............................................................. 384 to 2048 bytes Package 80P6N-A ..................................... 0.8 mm-pitch plastic molded QFP 80D0 ........................ 0.8 mm-pitch ceramic LCC (EPROM version) ROM size (byte) External ROM 60K Being planned M38078S Under development M38079EF Being planned 48K Being planned M38078MC 32K 28K 24K 20K 16K 12K 8K Mass product Mass product M38073M4 M38073E4 M38077M8 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 RAM size (byte) Note : Products under development or planning : the development schedule and specifications may be revised without notice. Fig. 4. Memory expansion plan Currently supported products are listed below. Table 3. List of supported products Product M38073M4-XXXFP M38073E4-XXXFP M38073E4FP M38073E4FS (P) ROM size (bytes) ROM size for User () 16384 (16254) 512 80P6N-A 80D0 Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version RAM size (bytes) Package Remarks As of May 1996 6 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3807 group uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine instructions or the SERIES 740 CPU Mode Register The CPU mode register contains the stack page selection bit and processor mode bits. The CPU mode register is allocated at address 003B16. b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available Stack page selection bit 0 : 0 page 1 : 1 page XCOUT drivability selection bit 0 : Low drive 1 : High drive Port XC switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function Main clock (XIN-XOUT) stop bit 0 : oscillating 1 : stopped Main clock division ratio selection bits b7 b6 0 0 : = f(XIN)/2 (high-speed mode) 0 1 : = f(XIN)/8 (middle-speed mode) 1 0 : = f(XCIN)/2 (low-speed mode) 1 1 : Not available Fig. 5. Structure of CPU mode register 7 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory Special function register (SFR) area The special function register (SFR) area in the zero page contains control registers such as I/O ports and timers. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. Special page ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the reset is user area for storing programs. The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. RAM area RAM capacity (byte) Address XXXX16 000016 SFR area 004016 RAM 010016 Zero page 192 256 384 512 640 768 896 1024 1536 2048 ROM area ROM capacity (byte) 00FF16 013F16 01BF16 023F16 02BF16 033F16 03BF16 043F16 063F16 083F16 XXXX16 Reserved area 084016 Not used Address YYYY16 Address ZZZZ16 4096 8192 12288 16384 20480 24576 28672 32768 36864 40960 45056 49152 53248 57344 61440 F00016 E00016 D00016 C00016 B00016 A00016 900016 800016 700016 600016 500016 400016 300016 200016 100016 F08016 E08016 D08016 C08016 B08016 A08016 908016 808016 708016 608016 508016 408016 308016 208016 108016 ROM YYYY16 Reserved ROM area (128 byte) ZZZZ16 FF0016 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Special page Fig. 6. Memory map diagram 8 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C16 001D16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Port P8 (P8) Port P8 direction register (P8D) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003316 Timer X (low-order) (TXL) Timer X (high-order) (TXH) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer 1 (T1) Timer 2 (T2) Timer 3 (T3) Timer X mode register (TXM) Timer Y mode register (TYM) Timer 123 mode register (T123M) Real time port register (RTP) Real time port control register 0 (RTPCON0) Real time port control register 1 (RTPCON1) Real time port control register 2 (RTPCON2) Real time port control register 3 (RTPCON3) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Timer B (low-order) (TBL) Timer B (high-order) (TBH) D-A control register (DACON) A-D control register (ADCON) A-D conversion register (AD) D-A1 conversion register (DA1) D-A2 conversion register (DA2) D-A3 conversion register (DA3) D-A4 conversion register (DA4) Interrupt edge selection register (INTEDGE) Timer XY control register (TXYCON) Port P2P3 control register (P2P3C) Pull-up control register (PULL) Watchdog timer control register (WDTCON) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register 1 (SIO2CON1) Serial I/O2 control register 2 (SIO2CON2) Serial I/O2 register (SIO2) 003416 003516 003616 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Interrupt control register 2(ICON2) Fig. 7. Memory map of special function register (SFR) 9 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O Ports [Direction Registers] PiD The 3807 group has 68 programmable I/O pins arranged in nine individual I/O ports (P0--P5, P60--P62, P65 and P7--P8). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When "0" is written to the bit corresponding to a pin, that pin becomes an input pin. When "1" is written to that pin, that pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input (the bit corresponding to that pin must be set to "0") are floating and the value of that pin can be written to. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. [Pull-up Control Register] PULL Ports P0, P1 and P2 have built-in programmable pull-up resistors. The pull-up resistors are valid only in the case that the each control bit is set to "1" and the corresponding port direction registers are set to input mode. (1) CMOS/TTL input level selection Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32. The input level is selected by P2*P32 input level selection bit (b7) of the port P2P3 control register (address 001516). When the bit is set to "0", CMOS input level is selected. When the bit is set to "1", the TTL input level is selected. After this bit is re-set, its initial value depends on the state of the CNVss pin. When the CNVss pin is connected to Vss, the initial value becomes "0". When the CNVss pin is connected to Vcc, the initial value becomes "1". (2) Notes on STP instruction execution Make sure that the input level at each pin is either 0V or to Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate. b7 b0 Port P2P3 control register (P2P3C : address 001516) P34 Clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bit 000: 001: f(XCIN) 010: "L" fixed output 011: "L" fixed output (f(XCIN) in low-speed mode) 100: f(XIN) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read) P2 * P32 input level selection bit 0: CMOS level input 1: TTL level input Fig. 8. Structure of Port P2P3 control register b7 b0 Pull-up control register (PULL : address 001616) P00--P03 pull-up control bit P04,P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit P10--P13 pull-up control bit P14--P17 pull-up control bit P20--P23 pull-up control bit P24--P27 pull-up control bit 0: No pull-up 1: Pull-up Fig. 9. Structure of Pull-up control register 10 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 4. List of I/O port functions (1) Pin P00-P07 P10-P17 P20-P27 Name Port P0 Port P1 Port P2 Input/Output Input/output, individual bits I/O Format Non-Port Function Related SFRs Ref.No. (1) CMOS compatible input level Address low-order byte output CPU mode register CMOS 3-state output Address high-order byte output Pull-up control register CMOS/TTL input level CMOS 3-state output Data bus I/O CPU mode register Pull-up control register Port P2P3 control register CPU mode register Real time port control register CPU mode register Port P2P3 control register CPU mode register CPU mode register Port P2P3 control register CPU mode register CPU mode register P30/RTP6, P31/RTP7 P32 P33 P34/CKOUT P35-P37 Port P3 CMOS compatible input level Real time port output CMOS 3-state output CMOS/TTL input level Control signal input CMOS 3-state output CMOS compatible input level Control signal output CMOS 3-state output Clock output, output Control signal I/O Sub-clock generating circuit (2) (3) (4) (3) (5) (6) (7) (8) (9) (10) (11) (12) (22) (7) (13) (14) (15) (16) P40/XCOUT, Port P4 P41/XCIN P42/INT0, P43/INT1 P44/RXD, P45/TXD, P46/SCLK1, P47/SRDY1 P50/TOUT P51/SCMP2/ INT2 P52/INT3, P53/INT4 Port P5 External interrupt input Interrupt edge selection register Timer X, Timer Y function input Serial I/O1 function I/O Serial I/O1 control register UART control register Timer 2 output External interrupt input Serial I/O2 function I/O External interrupt input Real time port trigger input (INT4) Timer X, Timer Y function I/O D-A conversion output A-D conversion input Input CMOS compatible input level Analog comparator input pin A-D conversion input Analog comparator reference voltage input pin A-D conversion input CMOS compatible input level D-A converter power source CMOS 3-state output input A-D conversion input Serial I/O2 function I/O Timer 123 mode register Interrupt edge selection register Serial I/O2 control register Interrupt edge selection register Timer X mode register Timer Y mode register D-A control register A-D control register A-D control register P54/CNTR0 P55/CNTR1 P56/DA1, P57/DA2 P60/AN5-- Port P6 P62/AN7 P63/CMPIN/ AN8 P64/CMPREF/ AN9 P65/DAVREF/ AN10 P70/SIN2, P71/SOUT2, P72/SCLK2 P73/SRDY2/ ADT/AN0 P74/AN1-- P77/AN4 Port P7 Input/output, individual bits A-D control register (17) Serial I/O2 control register (18) (19) (20) (21) Serial I/O2 function I/O A-D trigger input A-D conversion input A-D conversion input Serial I/O2 control register A-D control register A-D control register (15) 11 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 5. List of I/O port functions (2) Pin P80/DA3/ AN11 P81/DA4/ AN12 P82/RTP0-- P87/RTP5 Name Port P8 Input/Output Input/output, individual bits I/O Format Non-Port Function Related SFRs D-A control register A-D control register Ref.No. (14) CMOS compatible input level D-A conversion output CMOS 3-state output A-D conversion input Real time port output Real time port control register (23) Note1 : For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections. 2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate. 12 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Ports P0--P2 Pull-up control (2) Ports P30,P31 Real time port output selection bit Direction register Direction register Data bus Port latch Data bus Port latch Data for real time port *1 (3) Ports P32,P33,P35--P37 Direction register (4) Port P34 Clock output control Direction register Data bus Port latch Data bus Port latch *1 Clock output (5) Port P40 Port XC switch bit Direction register (6) Port P41 Port XC switch bit Direction register Data bus Port latch Data bus Port latch Oscillator Port P41 Port XC switch bit Sub-clock oscillating circuit input (7) Ports P42,P43,P52,P53 Direction register (8) Port P44 Serial I/O1 enable bit Receive enable bit Direction register Data bus Port latch Data bus Port latch Interrupt input Timer X input (P42) Timer Y input (P43) RTP trigger input (P53) except P52 *1 Either CMOS input level or TTL input level can be selected as an input level for ports P20 to P27 and P32 by P2*P32 input level selection bit. serial I/O1 input Fig. 10. Port block diagram (1) 13 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (9) Port P45 P45/TXD P-channel output disable bit Serial I/O1 enable bit Transmit enable bit Direction register (10) Port P46 Serial I/O1 synchronous clock selection bit Serial I/O1 enable bit Serial I/O1mode selection bit Serial I/O1enable bit Direction register Data bus Port latch Data bus Port latch Serial I/O1 output Serial I/O1 clock output Serial I/O1 external clock input (11) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit SRDY1 output enable bit Direction register (12) Port P50 Direction register Data bus Port latch Data bus Port latch TOUT output control bit Timer 2 output Serial I/O1 ready output (13) Ports P54,P55 Direction register (14) Ports P56,P57,P80,P81 Direction register Data bus Port latch Data bus Port latch Timer X, Timer Y operating mode bits "001" "100" "101" "110" Timer output CNTR0, CNTR1 interrupt input D-A conversion output DA1 output enable bit (P56) DA2 output enable bit (P57) DA3 output enable bit (P80) DA4 output enable bit (P81) A-D conversion input Analog input pin selection bit except P56,P57 (15) Ports P60--P62,P74--P77 Direction register (16) Ports P63,P64 Data bus Port latch Data bus A-D conversion input Analog input pin selection bit A-D conversion input Analog input pin selection bit Analog comparator input Fig. 11. Port block diagram (2) 14 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (17) Port P65 Direction register (18) Port P70 Direction register Data bus Port latch Data bus Port latch D-A conversion power source input A-D conversion input Analog input pin selection bit Serial I/O2 input (19) Port P71 P71/SOUT2 P-channel output disable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register (20) Port P72 Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register P72/SCLK2 P-channel output disable bit Data bus Port latch Data bus Port latch Serial I/O2 clock output Serial I/O2 clock output Serial I/O2 external clock input (21) Port P73 SRDY2 output enable bit Direction register (22) Port P51 Serial I/O2 I/O comparison signal control bit Direction register Data bus Port latch Data bus Port latch Serial I/O2 ready output AD external trigger valid bit A-D trigger interrupt input A-D conversion input Analog input pin selection bit Serial I/O2 I/O comparison signal output Interrrupt input (23) Ports P82--P87 Real time port output selection bit Direction register Data bus Port latch Data for real time port Fig. 12. Port block diagram (3) 15 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupts Interrupts occur by twenty sources: eight external, eleven internal, and one software. (1) Interrupt Control Each interrupt except the BRK instruction interrupt have both an interrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding interrupt request and enable bits are "1" and the interrupt disable flag is "0". Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. (2) Interrupt Operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack 3. Concurrently with the push operation, the interrupt jump destination address is read from the vector table into the program counter. 4. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. sNotes on Use When the active edge of an external interrupt (INT0--INT4, CNTR0 or CNTR1) is set or the timer /INT interrupt source and the ADT/ A-D conversion interrupt source are changed, the corresponding interrupt request bit may also be set. Therefore, please take following sequence: (1) Disable the external interrupt which is selected. (2) Change the active edge in interrupt edge selection register (in case of CNTR0: Timer X mode register ; in case of CNTR1: Timer Y mode register). (3) Clear the set interrupt request bit to "0." (4) Enable the external interrupt which is selected. 16 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table. 6. Interrupt vector addresses and priority Interrupt Source Priority Reset (Note 2) INT0 INT1 Serial I/O1 receive Serial I/O1 transmit Timer X Timer Y INT3 1 2 3 4 5 6 7 8 Vector Addresses (Note 1) High FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 Low FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT0 input At detection of either rising or falling edge of INT1 input At completion of serial I/O1 data receive At completion of serial I/O1 data transmit shift or when transmit buffer is empty At timer X underflow At timer Y underflow At detection of either rising or falling edge of INT3 input Timer 2 INT4 At timer 2 underflow At detection of either rising or falling edge of INT4 input At timer 3 underflow At detection of either rising or falling edge of CNTR0 input At detection of either rising or falling edge of CNTR1 input At completion of serial I/O2 data transmit and receive At detection of either rising or falling edge of INT2 input Timer 1 Timer A Timer B A-D conversion ADT At timer 1 underflow At timer A underflow At timer B underflow At completion of A-D conversion At falling edge of ADT input Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O1 is selected Valid when serial I/O1 is selected Remarks External interrupt (active edge selectable) Valid when INT3 interrupt is selected Valid when timer 2 interrupt is selected External interrupt (active edge selectable) Valid when INT4 interrupt is selected Valid when timer 3 interrupt is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when serial I/O2 is selected External interrupt (active edge selectable) Valid when INT2 interrupt is selected Valid when timer 1 interrupt is selected 9 FFED16 FFEC16 Timer 3 CNTR0 CNTR1 Serial I/O2 INT2 10 11 12 13 FFEB16 FFE916 FFE716 FFE516 FFEA16 FFE816 FFE616 FFE416 14 15 16 FFE316 FFE116 FFDF16 FFE216 FFE016 FFDE16 BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Valid when A-D interrupt is selected External interrupt(valid at falling) Valid when ADT interrupt is selected and when A-D external trigger is selected. Non-maskable software interrupt Note1 : Vector addresses contain interrupt jump destination addresses. 2 : Reset function in the same way as an interrupt with the highest priority. 17 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig. 13. Interrupt control b7 b0 Interrupt edge selection register (INTEDGE : address 003A16) INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit INT4 interrupt edge selection bit Timer 1/INT2 interrupt source bit Timer 2/INT3 interrupt source bit Timer 3/INT4 interrupt source bit 0 : Falling edge active 1 : Rising edge active 0 : INT interrupt selected 1 : Timer interrupt selected b7 b0 Interrupt request register 2 (IREQ2 : address 003D16) CNTR0 interrupt request bit CNTR1 interrupt request bit Serial I/O2 interrupt request bit Timer 1/INT2 interrupt request bit Timer A interrupt request bit Timer B interrupt request bit ADT/AD conversion interrupt request bit Not used (returns "0" when read) 0 : No interrupt request issued 1 : Interrupt request issued b7 b0 Interrupt request register 1 (IREQ1 : address 003C16) INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2/INT3 interrupt request bit Timer 3/INT4 interrupt request bit b7 b0 Interrupt control register 1 (ICON1 : address 003E16) INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2/INT3 interrupt enable bit Timer 3/INT4 interrupt enable bit b7 b0 Interrupt control register 2 (ICON2 : address 003F16) CNTR0 interrupt enable bit CNTR1 interrupt enable bit Serial I/O2 interrupt enable bit Timer 1/INT2 interrupt enable bit Timer A interrupt enable bit Timer B interrupt enable bit ADT/AD conversion interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0 : Interrupt disabled 1 : Interrupt enabled Fig. 14. Structure of Interrupt-related registers 18 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timers The 3807 group has seven timers : four 16-bit timers (Timer X, Timer Y, Timer A, and Timer B) and three 8-bit timers (Timer 1, Timer 2, and Timer 3). All timers are down-counters. When the timer reaches either "0016" or "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. When a timer underflows, the interrupt request bit corresponding to that timer is set to "1." Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read from the high-order byte first. When writing to 16-bit timer, write to the loworder byte first. The 16-bit timer cannot perform the correct operation when reading during write operation, or when writing during read operation. Timers A and B are real time output port timers. For details, refer to the section "Real time output port". qTimer X, Timer Y Timer X and Y are independent 16-bit timers which can select enable seven different operation modes each by the setting of their mode registers. The related registers of timer X and Y are listed below. The following register abbreviations are used: * Timer XY control register (TXYCON: address 001416) * Port P4 direction register (P4D: address 000916) * Port P5 direction register (P5D: address 000B16) * Timer X (low-order) (TXL: address 002016) * Timer X (high-order) (TXH: address 002116) * Timer Y (low-order) (TYL: address 002216) * Timer Y (high-order) (TYH: address 002316) * Timer X mode register (TXM: address 002716) * Timer Y mode register (TYM: address 002816) * Interrupt edge selection register (INTEDGE: address 003A16) * Interrupt request register 1 (IREQ1: address 003C16) * Interrupt request register 2 (IREQ2: address 003D16) * Interrupt control register 1 (ICON1: address 003E16) * Interrupt control register 2 (ICON2: address 003F16) For details, refer to the structures of each register. The following is an explanation of the seven modes: (1) Timer * event counter mode Timer mode * Mode selection This mode can be selected by setting "000" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). A count source is selected by the following bit. Timer X count source selection bit (bits 7 and 6) of TXM Timer Y count source selection bit (bits 7 and 6) of TYM * Interrupt When an underflow is generated, the corresponding timer X interrupt request bit (b4) or timer Y interrupt request bit (b5) of IREQ1 is set to "1". * Explanation of operation After reset release, timer X stop control bit (b0) and timer Y stop control bit (b1) of TXYCON are set to "1"and the timer stops. During timer stop, a timer value written to the timer X or timer Y is set by writing data to the corresponding timer latch and timer at the same time. The timer operation is started by setting the bits 0 or 1 of TXYCON to "0". When the timer reaches "000016", an underflow occurs with the next count pulse. Then the contents of the timer latch is reloaded into the timer and the timer continues down-counting. For changing a timer value during count operation, a latch value must be changed by writing data only to the corresponding latch first. Then the timer is reloaded with the new latch value at the next underflow. Event counter mode * Mode selection This mode can be selected by the following sequence. 1. Set "000" to the timer X operating mode bit (bits 2 to 0) of TXM, or to the timer Y operating mode bit (bits 2 to 0) of TYM. 2. Select an input signal from the CNTR0 pin (in case of timer X ; set "11" to bits 7 and 6 of TXM), or from the CNTR1 pin (in case of timer Y ; set "11" to bits 7 and 6 of TYM) as a count source. The valid edge for the count operation is selected by the CNTR0/ CNTR1 active edge switch bit (b5) of TXM or TYM: if set to "0", counting starts with the rising edge or if set to "1", counting starts with the falling edge. * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. * Explanation of operation The operation is the same as already explained for the timer mode. In this mode, the double-function port of CNTR0/CNTR1 pin must be set to input. Figure 19 shows the timing chart for the timer * event counter mode. (2) Pulse output mode * Mode selection This mode can be selected by setting "001" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. * Explanation of operation Counting operation is the same as in timer mode. Moreover the pulse which is inverted each time the timer underflows is output from CNTR0/CNTR1 pin. When the CNTR0/CNTR1 active edge switch bit (b5) of TXM or TYM is "0", output starts with "H" level. When set to "1", output starts with "L" level. 19 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER sPrecautions Set the double-function port of CNTR0/CNTR1 pin to output in this mode. [During timer operation stop] The output from CNTR0/CNTR1 pin is initialized to the level set through CNTR0/CNTR1 active edge switch bit. [During timer operation enabled] When the value of the CNTR0/CNTR1 active edge switch bit is written over, the output level of CNTR0/CNTR1 pin is inverted. Figure 20 shows the timing chart of the pulse output mode. (3) Pulse period measurement mode * Mode selection This mode can be selected by setting "010" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bits 0 or 1 of IREQ2 is set to "1" synchronously to pulse period measurement completion. * Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse periods to be measured. When bit 5 of the TXM or TYM is set to "0", the timer counts during the interval of one falling edge of CNTR0/ CNTR1 pin input until the next falling edge of input. If bits 5 are set to "1", the timer counts during the interval of one rising edge until the next rising edge. [During timer operation enabled] The pulse period measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement start/stop is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF16" is set to the timer. The measured value is held until the next measurement completion. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse periods). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. The timer is set to "FFFF16" when the timer either underflows or a valid edge of pulse period measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 19 shows the timing chart of the pulse period measurement mode. (4) Pulse width measurement mode * Mode selection This mode can be selected by setting "011" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. Bit 0 or 1 of IREQ2 is set to "1" synchronously to pulse width measurement completion. * Explanation of operation [During timer operation stop] Select the count source. Next, select the interval of the pulse widths to be measured. When bit 5 of TXM or TYM is set to "1", the timer counts during the interval of one falling edge of CNTR0/CNTR1 pin input until the next rising edge of input ("L" interval). If bit 5 is set to "0", the timer counts during the interval of one rising edge until the next falling edge ("H" interval). [During timer operation enabled] The pulse width measurement starts by setting bit 0 or 1 of TXYCON to "0" and the timer counts down from the value that was set to the timer before the start of measurement. When a valid edge of measurement completion is detected, the 1's complement of the timer value is written to the timer latch and "FFFF16" is set to the timer. Furthermore when the timer underflows, a timer X/Y interrupt request occurs and "FFFF16" is set to the timer. The measured value is held until the next measurement completion. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to input in this mode. A read-out of timer value is impossible in this mode. The timer is written to only during timer stop (no measurement of pulse widths). Since the timer latch in this mode is specialized for the read-out of measured values, do not perform any write operations during measurement. The timer value is set to "FFFF16" when the timer either underflows or a valid edge of pulse widths measurement is detected. Due to that, the timer value at the start of measurement depends on the timer value before the start of measurement. Figure 20 shows the timing chart of the pulse width measurement mode. (5) Programmable waveform generation mode * Mode selection This mode can be selected by setting "100" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2, f(XIN)/16, or f(XCIN) can be selected as the count source. In low-speed mode the count source is f(XCIN). * Interrupt The interrupt generation at underflow is the same as already 20 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER explained for the timer mode. * Explanation of operation Counting operation is the same as in timer mode. Moreover the timer outputs the data set in the corresponding output level latch (bit 4 of TXM or TYM) to CNTR0/CNTR1 pin each time the timer underflows. After the timer underflows, the generation of optional waveform from CNTR0/CNTR1 pin is possible through a change of values in the output level latch and timer latch. sPrecautions Set the double-function port of CNTR0/CNTR1 pin to output in this mode. Figure 23 shows the timing chart of the programmable waveform generation mode. (6) Programmable one-shot generating mode * Mode selection This mode can be selected by setting "101" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. * Interrupt The interrupt generation at underflow is the same as already explained for the timer mode. The one-shot generating trigger condition must be set to the INT0 interrupt edge selection bit (b0) and INT1 interrupt edge selection bit (b1) of INTEDGE. Setting these bits to "0" causes the interrupt request being triggered by a falling edge, setting them to "1" causes the interrupt request being triggered by a rising edge. The INT0 interrupt request bit (b0) and INT1 interrupt request bit (b1) of IREQ1 are set to "1" by detecting the active edge of the INT pin. * Explanation of operation For a "H" one-shot pulse, set bit 5 of TXM, TYM to "0". [During timer operation stop] The output level of CNTR0/CNTR1 pin is initialized to "L" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "H" is output, and at underflow "L" is output from CNTR0/CNTR1 pin. For a "L" one-shot pulse set bit 5 of TXM, TYM to "1". [During timer operation stop] The output level of CNTR0/CNTR1 pin is initialized to "H" at mode selection. Set the one-shot pulse width to TXH, TXL, TYH, TYL. A trigger generation during timer stop (input signal to INT0/INT1 pin) is invalid. [During timer operation enabled] When a trigger generation is detected, "L" is output, and at underflow "H" is output from CNTR0/CNTR1 pin. sPrecautions * Set the double-function port of CNTR0/CNTR1 pin to output and the double-function port of INT0/INT1 pin to input in this mode. * This mode is unused in low-speed mode. * During one-shot generation permission or one-shot generation the output level from CNTR0/CNTR1 pin changes if the value of the CNTR0/CNTR1 active edge switch bit is inverted. Figure 24 shows the timing chart of the programmable one-shot generating mode. (7) PWM mode * Mode selection This mode can be selected by setting "110" to the following bits. Timer X operating mode bit (bits 2 to 0) of TXM Timer Y operating mode bit (bits 2 to 0) of TYM * Count source selection In high- or middle-speed mode, f(XIN)/2 or f(XIN)/16 can be selected as the count source. * Interrupt With a rising edge of CNTR0/CNTR1 output, the timer X interrupt request bit (b4) and timer Y interrupt request bit (b5) of IREQ1 are set to "1". * Explanation of operation PWM waveform is output from CNTR0 pin (in case of timer X) or from CNTR1 pin (in case of timer Y). The "H" interval of PWM waveform is determined by the setting value m (m=0 to 255) of TXH and TYH and the "L" interval of PWM waveform is determined by the setting value n (n=0 to 255) of TXL and TYL. The PWM cycles are: PWM cycle time = (m+n)*ts PWM duty = m/(m+n) where: ts: period of timer X/timer Y count source [During count operation stop] When a timer value is set to TXL, TXH, TYL, TYH by writing data to timer and timer latch at the same time. When setting this value, the output of CNTR0/CNTR1 pin is initialized to the "H" level. [During count operation enabled] By setting the bit 0 or 1 of TXYCON to "0", an "H" interval of TXH or TYH is output first, and after that a "L" level interval of TXL or TYL are output next. These operations are repeated continuously. The PWM output is changed after the underflow by setting a timer value, which is set by writing data to the timer latch only, to TXL, TXH, TYL, TYH. sPrecautions * Set the double-function port of CNTR0/CNTR1 pin to output in this mode. * This mode is unused in low-speed mode. * When the PWM "H" interval is set to "0016", PWM output is "L". * When the PWM "L" interval is set to "0016", PWM output is "H". * When the PWM "H" interval and "L" interval are set to "0016", PWM output is "L". * When a PWM "H" interval or "L" interval is set to "0016" at least for a short time, timer X/timer Y interrupt request does not occur. * When the value set to the timer latch is "0016", the value is undefined since the timer counts down by dummy count operation. Figure 23 shows the timing chart of the PWM mode. 21 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER sPrecautions regarding all modes * Timer X, timer Y writing control One of the following operation is selected by bit 3 of TXM or TYM for timer X or timer Y. Writing data to the corresponding latch and timer at the same time Writing data to only corresponding latch When the operation "writing data to only corresponding latch" is selected, the value is set to the timer latch by writing a value to timer X/Y address and a timer is renewed at the next underflow. After releasing a reset, "writing the corresponding latch and timer at the same time" is selected. When a value is written to timer X/Y address, a value is set to a timer and a timer latch at the same time. When "writing data to only corresponding latch" is selected, if writing to a reload latch and an underflow are performed at the same timing, the timer value is undefined. * Timer X, timer Y read control In pulse period measurement mode and pulse width measurement mode the timer value cannot be read-out. In all other modes readout operations without effect to count operations/stops are possible. However, the timer latch value cannot be read-out. * Precautions regarding the CNTR0/CNTR1 active edge switch bit and the INT0/INT1 interrupt edge selection bit: The CNTR0/CNTR1 active edge switch bit and the INT0/INT1 interrupt edge selection bit settings have an effect also on each interrupt active edge. 22 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CNTR0 active edge switch bit Programmable one-shot "1" P42/INT0 Programmable one-shot generating mode PWM mode PWM mode PWM generating circuit Programmable one-shot generating circuit "0" generating mode Data bus INT0 interrupt request Programmable waveform generating mode Output level latch D T pulse output mode S Q T "001" "100" "101" "110" Timer X operating mode bits Timer X latch (low-order) P54 latch Timer X (low-order) Q CNTR0 active edge switch bit "0" "1" Pulse output mode Q Timer X latch (high-order) Timer X (high-order) Timer X interrupt request P54 direction register Pulse period measurement mode Pulse width measurement mode Edge detection circuit CNTR0 interrupt request "1" P54/CNTR0 f(XIN)/2 f(XIN)/16 f(XCIN) "0" CNTR0 active edge switch bit Timer X stop control bit Timer X count source selection bits P43/INT1 Programmable one-shot generating mode CNTR1 active edge switch bit Programmable one-shot "1" generating mode Programmable one-shot generating circuit "0" PWM mode PWM mode PWM generating circuit INT1 interrupt request Programmable waveform generating mode Output level latch D T Q Pulse output mode CNTR1 active edge switch bit "0" "1" Pulse output mode S Q T "001" "100" "101" "110" Timer Y operating mode bits P55 latch P55 direction register Timer Y latch (low-order) Timer Y (low-order) Q Timer Y latch (high-order) Timer Y (high-order) Timer Y interrupt request Pulse period measurement mode Pulse width measurement mode Edge detection circuit CNTR1 interrupt request "1" P55/CNTR1 f(XIN)/2 f(XIN)/16 f(XCIN) "0" CNTR1 active edge switch bit Timer Y stop control bit Timer Y count source selection bits Fig. 15. Block diagram of Timer X and Timer Y 23 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 b7 b0 Timer X mode register (TXM : address 002716) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer * event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output CNTR0 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse period measurement mode ; measures between two falling edges * Pulse width measurement mode ; measures "H" periodes * Programmable one-shot generating mode ; after start at "L" level, output a "H" pulse (interrupt request is triggered on falling edge) 1 : * Eevent counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse period measurement mode ; measures between two rising edges * Pulse width measurement mode ; measures "L" periodes * Programmable one-shot generating mode ; after start at "H" level, output a "L" pulse (interrupt request is triggered on rising edge) Timer X count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR0 pin Timer Y mode register (TYM : address 002816) Timer Y operating mode bits b2 b1 b0 0 0 0 : Timer*event counter mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generating mode 1 0 1 : Programmable one-shot generating mode 1 1 0 : PWM mode 1 1 1 : Not used Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Output level latch 0 : "L" output 1 : "H" output CNTR1 active edge switch bit 0 : * Event counter mode ; counts rising edges * Pulse output mode ; output starts with "H" level * Pulse period measurement mode ; measures between two falling edges * Pulse width measurement mode ; measures "H" periodes * Programmable one-shot generating mode ; after start at "L" level, output a "H" pulse (interrupt request is triggered on falling edge) 1 : * Eevent counter mode ; counts falling edges * Pulse output mode ; output starts with "L" level * Pulse period measurement mode ; measures between two rising edges * Pulse width measurement mode ; measures "L" periodes * Programmable one-shot generating mode ; after start at "H" level, output a "L" pulse (interrupt request is triggered on rising edge) Timer Y count source selection bits b7 b6 0 0 : f(XIN)/2 0 1 : f(XIN)/16 1 0 : f(XCIN) 1 1 : Input signal from CNTR1 pin b7 b0 Timer XY control register (TXYCON : address 001416) Timer X stop control bit 0 : start counting 1 : stop counting Timer Y stop control bit 0 : start counting 1 : stop counting Not used (returns "0" when read) Fig. 16. Structure of Timer X mode register, Timer Y mode register, and Timer XY control register 24 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF16 TL 000016 TR TR TR TL: A value set to a timer latch TR: Timer interrupt request Fig. 17. Timing chart of Timer*Event counter mode FFFF16 TL 000016 TR TR TR TR Waveform output from CNTR0/CNTR1 pin CNTR CNTR TL: A value set to a timer latch TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit "0": output starts with "H" level, interrupt at falling edge Fig. 18. Timing chart of Pulse output mode 25 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 000016 T3 T2 T1 FFFF16 TR FFFF16+T1 T2 T3 FFFF16 TR Signal input from CNTR0/CNTR1 pin CNTR CNTR CNTR CNTR TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "1" measure from rising edge to rising edge; interrupt at rising edge Fig. 19 Timing chart of Pulse period measurement mode 000016 T3 T2 T1 FFFF16 TR TR FFFF16+T2 Signal input from CNTR0/CNTR1 pin CNTR TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "1" measure "L" width; interrupt at rising edge Fig. 20. Timing chart of Pulse width measurement mode T3 T1 CNTR CNTR 26 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FFFF16 T3 L T2 T1 000016 Signal output from CNTR0/CNTR1 pin L TR T1 T3 T2 TR TR TR CNTR CNTR L: Initial value of timer TR: Timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output starts with "L" level; interrupt at falling edge Fig. 21. Timing chart of Programmable waveform generating mode FFFF16 L TR Signal input from INT0/INT1 pin Signal output from CNTR0/CNTR1 pin TR TR L CNTR L CNTR L L: One-shot pulse width; timer latch value TR: timer interrupt request CNTR: CNTR0/CNTR1 interrupt request This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output a "H" pulse; interrupt at falling edge Fig. 22. Timing chart of Programmable one-shot generating mode 27 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ts Timer X/Timer Y count source Timer X/Timer Y PWM output signal m ! ts n ! ts (m+n) ! ts CNTR TR CNTR: CNTR0/CNTR1 interrupt request TR: Timer interrupt request PWM waveform (duty : m/(m + n) and period: (m + n) ! ts) is output m : the setting value of TXH/TYH (m = 0 to 255) n: the setting value of TXL/TYL (n = 0 to 255) ts: the period of timer X / timer Y count source TR This example's condition: CNTR0/CNTR1 active edge switch bit set to "0" output starts with "H" level; interrupt at falling edge Fig. 23. Timing chart of PWM mode 28 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER qTimer 1, Timer 2, Timer 3 Timer 1 to 3 are 8-bit timers for which the count source can be selected through timer 123 mode register. b7 b0 (1) Timer 2 write control Timer 2 write control bit (b2) of timer 123 mode register allows to select whether a value written to timer 2 is written to timer latch and timer synchronously or to the timer latch only. If only the timer latch is written to, the value is set only to the reloadlatch by writing a value to the timer address at that time. The content of timer is reloaded with the next underflow. Usually writing operation to the timer latch and timer synchronously is selected. And a value is written to the timer latch and timer synchronously when a value is written to the timer address. If only the timer latch is written to, it may occur that the value set to the counter is not constant, when the timing with which the reloadlatch is written to and the underflow timing is nearly the same. (2) Timer 2 output control When timer 2 output (TOUT) is enabled, inverted signals are output from TOUT pin each time timer 2 has underflow. For this reason, set the double-function port of TOUT pin to output mode. sPrecautions on timers 1 to 3 When the count source for timer 1 to 3 is switched, it may occur that short pulses are generated in count signals and that the timer count value shows big changes. When timer 1 output is selected as timer 2 or timer 3 count source, short pulses are generated to signals output from timer 1 through writing timer 1. Due to that, the count values for timer 2 and 3 may change very often. Therefore, when the count sources for timer 1 to 3 are set, set the values in order starting from timer 1. Timer 123 mode register (T123M : address 002916) TOUT output active edge switch bit 0 : start with "H" output 1 : start with "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 2 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 3 count source selection bit 0 : Timer 1 output 1 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) Timer 1 count source selection bits 00 : f(XIN)/16 (or f(XCIN)/16 in low-speed mode) 01 : f(XIN)/2 (or f(XCIN)/2 in low-speed mode) 10 : f(XCIN) 11 : Not available Not used (returns "0" when read) Fig. 24. Structure of Timer 123 mode register f(XIN)/16 (f(XCIN)/16 in low-speed mode) Timer 1 count source selection bits "00" Timer 1 latch (8) "01" f(XIN)/2 Timer 1 (8) (f(XCIN)/2 in low-speed mode) "10" f(XCIN) Data bus Timer 1 interrupt request Timer 2 interrupt request Timer 2 count source selection bit Timer 2 latch (8) "0" Timer 2 (8) "1" f(XIN)/16 (f(XCIN)/16 in low-speed mode) Timer 2 write control bit TOUT output TOUT output active control bit edge switch bit "0" QS P50/TOUT P50 direction register P50 latch "1" Q "0" T Timer 3 latch (8) Timer 3 (8) "1" Timer 3 count source selection bit Timer 3 interrupt request TOUT output control bit f(XIN)/16 (f(XCIN)/16 in low-speed mode) Fig. 25. Block diagram of Timer 29 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER qReal time output port The 3807 group has two on-chip sets of real time output ports (RTP). The two sets of real time output ports consist of two 16-bit timers A and B and eight 8-bit real time port registers. Synchronous to the reloading of timers A and B, the real time port register values are output from ports P82 to P87, P30 and P31. The real time port registers consist of 8-bit register 0 to 7. Each port with its corresponding bits is shown in figure 26. Timer A and timer B have each two 16-bit timer latches. Figure 26 shows the real time port block diagram and figure 27 and 28 show the structure of the real time port control registers 0 to 3. There are four operating modes for real time ports which are: 8 repeated load mode, 6 repeated load mode, 5 repeated load mode and one-shot pulse generating mode. Each operating mode can be set for timer A and timer B separately. However, switch modes during timer count stop. (1) 8 repeated load mode The output operation for each value of the real time port registers 7 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 8 repeated load operations as "7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 29 shows a timing chart of 8 repeated load mode. (2) 6 repeated load mode The output operation for each value of real time port registers 5 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 to 0. The real time port output pointer changes in sequence as a cycle of 6 repeated load operations as "5, 4, 3, 2, 1, 0, 5, 4, 3, 2, 1, 0, 5, 4, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 30 shows a timing chart of the 6 repeated load mode. (3) 5 repeated load mode The output operation for each value of real time port registers 4 to 0 is performed repeatedly in association with an alternate underflow of the corresponding timer latch 1 or 0. The real time port output pointer changes in sequence as a cycle of 5 repeated load operations as "4, 3, 2, 1, 0, 4, 3, 2, 1, 0, 4, 3, 2, 1, ...." The initial value at the generation of a start trigger can be specified by setting a value in the output pointer. Figure 31 shows a timing chart of the 5 repeated load mode. (4) One-shot pulse generation mode The output operation for each value of real time port registers 2 to 0 is performed only once in association with trigger generation and an underflow of timer latch 1 or 0. After a trigger is generated, the value of real time port register 1 is output from the real time output port and the output pointer value becomes "0002". At each underflow of the timer, the each value of real time port registers 0 and 2 is output in ascending sequence, then the operation is completed. After completion of the operation, the value of real time port register 2 is continuously output from the real time output port and the output pointer value continues to be "0012" until the next start trigger is generated. In this condition, the real time port function is in the wait status. When this mode is selected, the pointer value is not changed by writing a value into the output pointer. If external trigger is specified as trigger selection when this mode is selected, a rising and falling double edge trigger is generated regardless of the contents of the INT4 interrupt source bit (b7) of the interrupt edge selection register. Figure 32 shows a timing chart of the one-shot pulse generation mode. (5) Selection of timer interrupt mode The timer is a count-down system. The contents of the timer latch are reloaded by the count pulse subsequent to the moment when the contents of the counter becomes "000016". At the same time, the interrupt request bit corresponding to each timer is set to "1." The interrupt request corresponding to the value of the real time port output pointer can also be controlled. For controlling the interrupt request bit, refer to the item pertaining to the timer interrupt mode selection bit of the real time port control register 1,2 shown in figure 27 and 28. (6) Switch of timer count source The timer A and the timer B can select the system clock divided by 2 or 16 as a count source with the timer A, B count source selection bit (b0) of real time port control register 0. [Timer latches] Each of the timer A and the timer B has two 16-bit timer latches. Data is written into the 8 low-order bits and the 8 high-order bits in this order. When the high-order side has been written, the next latch is automatically specified. The writing pointer changes in sequence as "1, 0, 1, 0, 1, ...." The timer latch to be written first can be specified by setting the timer writing pointer. Data is not written directly into the timer A and the timer B. When reading the contents of the timer, the count value at that point of time is read. Read the high-order side first and then the low-order side. The low-order side value is read with the same timing as that for the high-order side value and held at the timer read latch. The data held state is released by reading the loworder side. At a reload operation of the timer A or the timer B. Timer latch 1 is reloaded as the initial value after a trigger is generated. After that, the timer latch is reloaded in sequence as "0, 1, 0, 1, ...." The timer latch value cannot be read out. [Start trigger] The operation of the real time port is started by a start trigger. When a start trigger is generated, the value of the real time port register specified by the output pointer (the value of real time port register 1 in the one-shot pulse generation mode) is output from the real time output port. The value of timer latch 1 is reloaded into the timer A or the timer B and the timer count A, B source stop bit is released, so that the timer count is started. After that, when the timer underflows, data is transferred from the real port register to the real time output port. As a start trigger, either internal trigger or external trigger can be selected by the timer A start trigger selection bit (b2) or timer B start trigger selection bit (b5) of real time port control register 0. 30 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER When the internal trigger is selected, a start trigger is generated by an input signal of the INT4 pin. The start trigger becomes a falling edge when the INT4 interrupt edge selection bit is "0" and a rising edge when this bit is "1". When the external trigger is selected in the one-shot pulse generation mode, the start trigger becomes a rising/falling double edge trigger regardless of the contents of the INT4 interrupt edge selection bit. [Real time port registers] RTP The data to be output to real time ports is written into 8 real time port registers 0 to 7. The correspondence between each bit of real time port registers and each port output is as follows : P31: bit 7 of real time port registers 7 to 0 P30: bit 6 of real time port registers 7 to 0 P87: bit 5 of real time port registers 7 to 0 P86: bit 4 of real time port registers 7 to 0 P85: bit 3 of real time port registers 7 to 0 P84: bit 2 of real time port registers 7 to 0 P83: bit 1 of real time port registers 7 to 0 P82: bit 0 of real time port registers 7 to 0 It can be selected for each bit by real time port control register 3 whether the output of each port is to be used as an ordinary I/O port or a real time port output. [Real time port data pointer] It can be optionally specified by the real time port data pointers A or B and the real time port data pointer A or B switching bit in which real time port register the output data is to be set or form which real time port register the data output is to be started. When writing output data into the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also write a value into the 3 bits of the real time port data pointers A, B. With this, the real time port register for writing will be specified. After that, when a value is written into the real time port register (address 002A16), the data is written into the specified real time port register and also the R/W pointer value is automatically decreased by 1. Then writing data is enabled into the next real time port register. A value of "0002" to "1112" can be set int the R/W pointer regardless of the operating mode specified by the timer A, B operating mode selection bit, and the R/W pointer value is automatically decreased by 1 by writing data into the real time port register. However, when a value becomes "0002", the R/W pointer value is decreased by 1 in the numeral range of stages to be used in each operating mode unless the R/W pointer is set again at the subsequent write operation to the real time port register. When "1112 (=7)" is set in the R/W pointer, the R/W pointer operation in each selected mode is as follows : *During 8 repeated load mode 76543210765... *During 6 repeated load mode 76543210543... *During 5 repeated load mode 76543210432.... *During one-shot pulse generation mode 76543210210.... When reading the real time port register, set the real time port data pointer A, B switch bit to "0" (select the R/W pointer) and also writing a value into the 3 bits of the real time port data pointer A, B to specify the real time port register for reading. After that, the value of the specified real time port register can be read by reading the real time port register (address 002A16). In this care, however, the R/W pointer value is not counted down automatically. Accordingly, to read another real time port register, rewrite the R/W pointer beforehand. To specify a read port register to be output to the real time output port, set the real time port data pointer A, B switch bit to "1" (select an output pointer) and also set a value in the 3 bits of the real time port data pointer A or B. When a start trigger is generated, data is output beginning with the real time port register set in the output pointer and the output pointer value is automatically decreased by 1. At each underflow of the timer A or timer B, the output pointer value is automatically decreased by 1. Regarding the case of the one-shot pulse generation mode, however, refer to the item pertaining to the one-shot pulse generation mode. When the real time port data pointer A to B has been read, only the output pointer can be read. sNotes regarding all modes *When the trigger is generated again during timer count operation, the operation is started from the beginning. In this case, put an interval of 3 cycles or more between the generation of a trigger and the generation of the next trigger, If the generation of the next trigger occurs almost concurrently with the underflow timing of the timer, the next real time output may not be performed normally. *To stop the timer count after generation of a start trigger, write "1" in the timer A, B count source stop bit of real time port control register 0 at an interval of 3 cycles or more of the timer count source. *To change the contents of the real time port data pointer A, B switch bit, the real time port data pointer must be specified simultaneously. Therefore, use the LDM/STA instruction instead of the SEB/CLB instruction. *If the timer A, B count source stop bit is changed ("1""0") by a start trigger between the read operation and the write operation of a read-modify-write instruction such as the SEB instruction which is used in real time port control register 0, the timer count will stop, having an effect on the real time output. An maximum interval of 2 cycles of the count source is required before the timer A, B count source stop bit is cleared to "0" which indicates the count operation state after a start trigger is generated regardless of whether the start trigger is an internal trigger or an external trigger. Accordingly, do not use the read-modify-write instruction for real time port control register 0 in this period. If a write operation for real time port control register 0 with any purpose other than stopping the timer count is performed concurrently with the generation of a start trigger, be sure to use such an instruction for writing "0" into the timer A, B count source stop bit as the LDM/STA instruction. Even if "0" is written into the timer A, B count source stop bit, the timer count remains in the stop state without change. *When the timing for writing to the high-order side reload latch is almost equal to the underflow timing, an undesirable value may be set in the timer A or timer B. *If the real time output port is selected by real time port control register 3 after resetting, "L" is output from this pin until a start trigger is generated. 31 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus XCIN "10" Main clock division ratio selection bits Timer A, B count source Timer A write pointer (1) Timer A 1H latch (8) Timer A 0H latch (8) Timer A 1L latch (8) Timer A 0L latch (8) 1/2 "0" selection bit XIN "00" "01" 1/16 "1" Timer A (16) Timer A interrupt request P50/RTP0 P31/RTP7 /PWM0 P31 latch PWM0eooO Real time output Real time port output selection bit (P31) Timer A count source stop bit Timer A read-out latch (8) Timer B write pointer (1) Timer B 1H latch (8) Timer B 1L latch (8) Timer B 0L latch (8) P31 direction register P30/RTP6 P30 latch PWM1eooO Real time output Real time port output selection bit (P30) Timer B 0H latch (8) Timer B (16) Timer B count source stop bit Timer B read-out latch (8) Timer B interrupt request P30 direction register P87/RTP5 P87 latch 7 Real time output Real time port output selection bit (P87) Real time port * port allocation selection bit "1" "0" 0 Real time port R/W pointer A (3) Real time port R/W pointer B (3) P87 direction register P86/RTP4 P86 latch Real time output Real time port output selection bit (P86) Real time port register 0 (8) Real time port register 1 (8) Real time port register 2 (8) Real time port register 3 (8) Real time port register 4 (8) Real time port register 5 (8) Real time port register 6 (8) Real time port register 7 (8) Real time port * port allocation selection bit P86 direction register P85/RTP3 P85 latch "1" "0" Real time port output pointer A (3) Real time port output pointer B (3) Real time output Real time port output selection bit (P85) Output latch (8) P85 direction register P84/RTP2 P84 latch Real time output Real time port output selection bit (P84) P84 direction register P83/RTP1 P83 latch When a start trigger bit is set to "1" (internal trigger is selected) When an external start trigger is generated (external trigger is selected) A timer latch value is loaded into the timer A timer latch value is loaded into the timer Real time output Real time port output selection bit (P83) operation P83 direction register P82/RTP0 P82 latch 0 1 stop at reset Timer count source stop bit is set to "1". Real time output Real time port output selection bit (P82) State transition of timer count source stop bit P82 direction register Fig. 26. Block diagram of Real time output port 32 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Real time port control register 0 (RTPCON0 : address 002B16) Timer A, B count source selection bit 0: f(XIN)/2 or f(XCIN)/2 1: f(XIN)/16 or f(XCIN)/16 Real time port * port allocation selection bit 0: 4-4 port division (P82 to P85 correspond to timer A; P86, P87, P30, P31 correspond to timer B) 1: 2-6 port division (P82 to P87 correspond to timer A; P30, P31 correspond to timer B) Timer A start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 3 to "1") 1: External trigger (trigger start by external input INT4) (note) Timer A start trigger bit ("0" at read-out) 0: Not triggered 1: Timer A start (when bit 2="0") Timer A count source stop bit 0: Count operation (when a start trigger is generated, "0" is set automatically) 1: Count stop Timer B start trigger selection bit 0: Internal trigger (trigger is generated by setting bit 6 to "1") 1: External trigger (trigger start by external input INT4) (note) Timer B start trigger bit ("0" at read-out) 0: Not triggered 1: Timer B start (when bit 5="0") Timer B count source stop bit 0: Count operation (when a start trigger is generated, "0" is set automatically) 1: Count stop Note: Rising or falling edge of external input can be switched by the INT4 interrupt edge selection bit of interrupt edge selection register (however, at one-shot pulse generating mode the timer is triggered at both rising and falling edge). b7 b0 Real time port control register 1 (RTPCON1 : address 002C16) Timer A operation mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode Real time port data pointer A switch bit ("1" at read-out ) 0: R/W pointer 1: Output pointer Timer A interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value "0002" 1: Interrupt request occurs regardless of RTP output pointer value Real time port data pointer A (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer A write pointer 0: indicates timer A0 latch 1: indicates timer A1 latch Fig. 27. Structure of Real time output port related register (1) 33 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7 b0 Real time port control register 2 (RTPCON2 : address 002D16) Timer B operating mode selection bit 00: 8 repeated load mode 01: 6 repeated load mode 10: 5 repeated load mode 11: One-shot pulse generating mode Real time port data pointer B switch bit ("1" at read-out ) 0: R/W pointer 1: Output pointer Timer B interrupt mode selection bit 0: Interrupt request occurs with RTP output pointer value "0002" 1: Interrupt request occurs regardless of RTP output pointer value Real time port data pointer B (output pointer value at read-out) 000: indicates real time port register 0 001: indicates real time port register 1 010: indicates real time port register 2 011: indicates real time port register 3 100: indicates real time port register 4 101: indicates real time port register 5 110: indicates real time port register 6 111: indicates real time port register 7 Timer B write pointer 0: indicates timer B0 latch 1: indicates timer B1 latch b7 b0 Real time port control register 3 (RTPCON3 : address 002E16) Real time port output selection bit (P82) 0: I/O port 1: Real time output port Real time port output selection bit (P83) 0: I/O port 1: Real time output port Real time port output selection bit (P84) 0: I/O port 1: Real time output port Real time port output selection bit (P85) 0: I/O port 1: Real time output port Real time port output selection bit (P86) 0: I/O port 1: Real time output port Real time port output selection bit (P87) 0: I/O port 1: Real time output port Real time port output selection bit (P30) 0: I/O port 1: Real time output port Real time port output selection bit (P31) 0: I/O port 1: Real time output port Fig. 28 Structure of Real time output port related register (2) 34 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer A operating mode selection bit: in case of 8 repeated load mode 4-4 port division Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Timer A count value A1 #7 1 A0 #6 1 A1 #5 0 A0 #4 0 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1 A1 #7 1 A0 #6 1 A1 #5 0 Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2 Port P85 / RTP3 0 1 1 1 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 Real time port output pointer A 7 6 5 4 3 2 1 0 7 6 5 4 #7--0: Data of real time port registers 7 to 0 Fig. 29. 8 repeated load mode operation Timer A operating mode selection bit: in case of 6 repeated load mode 4-4 port division (3 ports out of P82/RTP0 to P85/RTP3 are used) Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Timer A count value A1 #5 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1 A1 #5 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0 Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2 0 1 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 Real time port output pointer A 5 4 3 2 1 0 5 4 3 2 1 0 #5--0: Data of real time port registers 5 to 0 Fig. 30. 6 repeated load mode operation 35 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer A operating mode selection bit: in case of 5 repeated load mode 2-6 division (5 ports out of P82/RTP0 to P87/RTP5 are used) Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. Timer count source stop bit Timer A count value A1 #4 1 A0 #3 0 A1 #2 0 A0 #1 0 A1 #0 1 A0 #4 1 A1 #3 0 A0 #2 0 A1 #1 0 A0 #0 1 Port P82 / RTP0 Port P83 / RTP1 Port P84 / RTP2 Port P85 / RTP3 Port P86 / RTP4 Real time port output pointer A 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 1 1 0 0 0 1 1 4 3 2 1 0 4 3 2 1 0 4 #4--0: Data of real time port registers 4 to 0 Fig. 31. 5 repeated load mode operation Timer A operating mode selection bit: in case of one-shot pulse generating mode Synchronous to the start trigger the timer latch value is loaded into the timer and timer count operation starts. External start trigger input INT4 Timer count source stop bit Counting stops when timer A0 latch has underflow Counting stops when timer A0 latch has underflow Timer A count value A1 #1 A0 #0 1 #2 0 A1 #1 0 A0 #0 1 #2 0 Port P82 / RTP0 0 Port P83 / RTP1 Real time port output pointer A 1 1 0 1 1 0 0 2 1 0 2 1 #2--0: Data of real time port registers 2 to 0 Fig. 32. One-shot pulse generating mode operation 36 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O qSerial I/O1 Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer (baud rate generator) is also provided for baud rate generation during Serial I/O1 operation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit (b6) of the serial I/O1 control register to "1." For clock synchronous serial I/O, the transmitter and the receiver must use the same clock for serial I/O1 operation. If an internal clock is used, transmit/receive is started by a write signal to the Transmit/Receive buffer register (TB/RB) (address:001816). Data bus Address 001816 Receive buffer register P44/RXD Receive shift register Shift clock P46/SCLK1 Serial I/O1 synchronous clock selection bit Division ratio 1/(n+1) BRG count source selection bit f(XIN) XIN Baud rate generator 1/4 (f(XCIN) in low-speed mode) Address 001C16 1/4 P47/SRDY1 F/F Falling edge detector Shift clock P45/TXD Transmit shift register Transmit buffer register Address 001816 Data bus Clock control circuit Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 Clock control circuit Serial I/O 1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) Fig. 33. Block diagram of clock synchronous serial I/O1 Transmit/Receive shift clock (1/2--1/2048 of internal clock or external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY1 Write-in signal to transmit/receive buffer register (address 001816) TBE = 0 RBF = 1 TSC = 1 Overrun error (OE) detection TBE = 1 TSC = 0 Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig. 34. Operation of clock synchronous serial I/O1 function 37 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2) Asynchronous Serial I/O (UART) Mode Asynchronous serial I/O1 mode (UART) can be selected by clearing the Serial I/O1 mode selection bit (b6) of the Serial I/O1 control register to "0." Eight serial data transfer formats can be selected and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer (the two buffers have the same address in memory). Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the receive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next character is being received. Data bus Address 001816 Receive buffer register OE Character length selection bit 7 bit STdetector Receive shift register 8 bit PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit Serial I/O1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 UART control register Address 001B16 P44/RXD P46/SCLK1 f(XIN) BRG count source selection bit 1/4 (f(XCIN) in low-speed mode) Division ratio 1/(n+1) Baud rate generator Address 001C16 ST/SP/PA generator 1/16 Transmit shift register shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 P45/TXD Character length selection bit Transmit shift register Transmit buffer register Address 001816 Data bus Fig. 35. Block diagram of UART serial I/O1 Transmit or receive clock Write-in signal to transmit buffer register TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit SP ST D0 D1 SP * Generated at 2nd bit in 2-stop bit mode TBE=0 TBE=1 TSC=1* Read-out signal from receive buffer register RBF=0 RBF=1 Serial input RXD ST D0 D1 SP ST D0 D1 SP RBF=1 Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1,5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig. 36. Operation of UART serial I/O1 function 38 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER [Transmit Buffer Register/Receive Buffer Register] TB/RB (001816) The transmit buffer and the receive buffer are located in the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O 1 Status Register] SIO1STS (001916) The read-only serial I/O1 status register consists of seven flags (b0 to b6) which indicate the operating status of the serial I/O1 function and various errors. Three of the flags (b4 to b6) are only valid in UART mode. The receive buffer full flag (b1) is cleared to "0" when the receive buffer is read. The error detection is performed at the same time data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A writing to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (b3 to b6, respectively). Writing "0" to the serial I/O1 enable bit (SIOE : b7 of the serial I/O1 control register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to "0" at reset, but if the transmit enable bit (b4) of the serial I/O1 control register has been set to "1", the transmit shift register shift completion flag (b2) and the transmit buffer empty flag (b0) become "1." [Serial I/O1 Control Register] SIO1CON (001A16) The serial I/O1 control register contains eight control bits for serial I/O1 functions. [UART Control Register] UARTCON (001B16) The UART control register consists of four control bits (b0 to b3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (b4) is always valid and sets the output structure of the P45/TxD pin. [Baud Rate Generator] BRG (001C16) The baud rate generator determines the baud rate for serial transfer. With the 8-bit counter having a reload register the baud rate generator divides the frequency of the count source by 1/(n+1), where n is the value written to the baud rate generator. b7 b0 Serial I/O1 status register (SIO1STS : address 001916) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O1 control register (SIO1CON : address 001A16) BRG count source selection bit (CSS) (f(XCIN) in low-peed mode) 0: f(XIN) 1: f(XIN)/4 ((XCIN)/4 in low-speed mode) Serial I/O1 synchronous clock selection bit (SCS) 0: BRG/ 4 (when clock synchronous serial I/O is selected) BRG/16 (UART is selected) 1: External clock input (when clock synchronous serial I/O is selected) External clock input/16 (UART is selected) SRDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P44 to P47 operate as ordinary I/O pins) 1: Serial I/O1 enabled (pins P44 to P47 operate as serial I/O pins) b7 b0 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity cheching disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P45/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return "1" when read) Fig. 37. Structure of serial I/O1 related register 39 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER qSerial I/O2 The serial I/O2 can be operated only as the clock synchronous type. As a synchronous clock for serial transfer, either internal clock or external clock can be selected by the serial I/O2 synchronous clock selection bit (b6) of serial I/O2 control register 1. The internal clock incorporates a dedicated divider and permits selecting 6 types of clock by the internal synchronous clock selection bit (b2, b1, b0) of serial I/O2 control register 1. Regarding SOUT2 and SCLK2 being output pins, either CMOS output format or N-channel open-drain output format can be selected by the P71/SOUT2, P72/SCLK2 P-channel output disable bit (b7) of serial I/O2 control register 1. When the internal clock has been selected, a transfer starts by a write signal to the serial I/O2 register (address 001F16). After completion of data transfer, the level of the SOUT2 pin goes to high impedance automatically but bit 7 of the serial I/O2 control register 2 is not set to "1" automatically. When the external clock has been selected, the contents of the serial I/O2 register is continuously sifted while transfer clocks are input. Accordingly, control the clock externally. Note that the SOUT2 pin does not go to high impedance after completion of data transfer. To cause the SOUT2 pin to go to high impedance in the case where the external clock is selected, set bit 7 of the serial I/O2 control register 2 to "1" when SCLK2 is "H" after completion of data transfer. After the next data transfer is started (the transfer clock falls), bit 7 of the serial I/O2 control register 2 is set to "0" and the SOUT2 pin is put into the active state. Regardless of the internal clock to external clock, the interrupt request bit is set after the number of bits (1 to 8 bits) selected by the optional transfer bit is transferred. In case of a fractional number of bits less than 8 bits as the last data, the received data to be stored in the serial I/O2 register becomes a fractional number of bits close to MSB if the transfer direction selection bit of serial I/O2 control register 1 is LSB first, or a fractional number of bits close to LSB if the said bit is MSB first. For the remaining bits, the previously received data is shifted. At transmit operation using the clock synchronous serial I/O, the SCMP2 signal can be output by comparing the state of the transmit pin SOUT2 with the state of the receive pin SIN2 in synchronization with a rise of the transfer clock. If the output level of the SOUT2 pin is equal to the input level to the SIN2 pin, "L" is output from the SCMP2 pin. If not, "H" is output. At this time, an INT2 interrupt request can also be generated. Select a valid edge by bit 2 of the interrupt edge selection register (address 003A16). [Serial I/O2 Control Registers 1, 2] SIO2CON1 / SIO2CON2 The serial I/O2 control registers 1 and 2 are containing various selection bits for serial I/O2 control as shown in Figure 40. b7 b0 Serial I/O2 control register 1 (SIO2CON1 : address 001D16) Internal synchronous clock selection bit b2 b1 b0 0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode) 0 0 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode) 0 1 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode) 0 1 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode) 1 1 0: f(XIN)/128 f(XCIN)/128 in low-speed mode) 1 1 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode) Serial I/O2 port selection bit 0: I/O port 1: SOUT2,SCLK2 output pin SRDY2 output enable bit 0: P73 pin is normal I/O pin 1: P73 pin is SRDY2 output pin Transfer direction selection bit 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit 0: External clock 1: Internal clock P71/SOUT2 ,P72/SCLK2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode ) b7 b0 Serial I/O2 control register 2 (SIO2CON2 : address 001E16) Optional transfer bits b2 b1 b0 0 0 0: 1 bit 0 0 1: 2 bit 0 1 0: 3 bit 0 1 1: 4 bit 1 0 0: 5 bit 1 0 1: 6 bit 1 1 0: 7 bit 1 1 1: 8 bit Not used ( returns "0" when read) Serial I/O2 I/O comparison signal control bit 0: P51 I/O 1: SCMP2 output SOUT2 pin control bit (P71) 0: Output active 1: Output high-impedance Fig. 38 Structure of Serial I/O2 control registers 1, 2 40 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 1/8 Internal synchronous clock selection bit XCIN Divider 1/16 "10" "00" "01" 1/32 1/64 1/128 1/256 Main clock division ratio selection bits (Note) Data bus XIN P73 latch "0" Serial I/O2 synchronous clock selection bit Synchronous circuit SCLK2 P73/SRDY2 "1" "0" SRDY2 "1" SRDY2 output enable bit External clock P72 latch "0" Optional transfer bits (3) Serial I/O counter 2 (3) Serial I/O2 interrupt request P72/SCLK2 "1" Serial I/O2 port selection bit P71 latch "0" P71/SOUT2 "1" Serial I/O2 port selection bit P70/SIN2 Serial I/O2 register (8) P51 latch "0" P51/SCMP2/INT2 "1" Serial I/O2 I/O comparison signal control bit D Q Note: Either high-speed, middle-speed or low-speed mode is selected by bits 6 and 7 of CPU mode register. Fig. 39. Block diagram of Serial I/O2 Transfer clock (Note 1) Write-in signal to serial I/O2 register (Note 2) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 D0 D1 . D2 D3 D4 D5 D6 D7 Receive enable signal SRDY2 Serial I/O2 interrupt request bit set Notes 1: When the internal clock is selected as a transfer clock, the f(XIN) clock division (f(XCIN) in low-speed mode) can be selected by setting bits 0 to 2 of serial I/O2 control register 1. 2: When the internal clock is selected as a transfer clock, the SCOUT2 pin has high impedance after transfer completion. Fig. 40. Timing chart of Serial I/O2 41 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SCMP2 SCLK2 SOUT2 SIN2 Judgement of I/O data comparison Fig. 41 SCMP2 output operation 42 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter [A-D Conversion Register] AD (address 003516) The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [A-D Control Register] ADCON The A-D control register controls the A-D conversion process. Bits 0 to 3 of this register select specific analog input pins. Bit 4 signals the completion of an A-D conversion. The value of this bit remains at "0" during an A-D conversion, then changes to "1" when the A-D conversion is completed. Writing "0" to this bit starts the A-D conversion. When bit 6, which is the AD external trigger valid bit, is set to "1", this bit enables A-D conversion at a falling edge of an ADT input. Set ports which is also used as ADT pins to input when using an A-D external trigger. Bit 5 is the ADVREF input switch bit. Writing "1" to this bit, this bit always causes ADVREF connection. Writing "0" to this bit causes ADVREF connection only during A-D conversion and cut off when A-D conversion is completed. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and ADVREF by 256, and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports AN12 to AN0 and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD conversion interrupt request bit to "1." Note that the comparator is constructed linked to a capacitor, so set f(XIN) to at least 500kHz during A-D conversion. Use a CPU system clock dividing the main clock XIN as the internal clock . sNote When the A-D external trigger is invalidated by the AD external trigger valid bit, any interrupt request is not generated at a fall of the ADT input. When the AD external trigger valid bit is set to "1" beforehand, A-D conversion is not started by writing "0" into the AD conversion completion bit and "0" is not written into the AD conversion completion bit. Do not set "0" in the AD conversion completion bit concurrently with the timing at which the AD external trigger valid bit is rewritten. Put an interval of at least 50 cycles to more of the internal clock between a start of A-D conversion and the next start of A-D conversion. b7 b0 A-D control register (ADCON : address 003416) Analog input pin selection bit 0000: P73/SRDY2/ADT/AN0 0001: P74/AN1 0010: P75/AN2 0011: P76/AN3 0100: P77/AN4 0101: P60/AN5 0110: P61/AN6 0111: P62/AN7 1000: P63/CMPIN/AN8 1001: P64/CMPREF/AN9 1010: P65/DAVREF/AN10 1011: P80/DA3/AN11 1100: P81/DA4/AN12 AD conversion completion bit 0: Conversion in progress 1: Conversion completed ADVREF input switch bit 0: OFF 1: ON AD external trigger valid bit 0: A-D external trigger invalid 1: A-D external trigger valid Interrupt source selection bit 0: Interrupt request at A-D conversion completed 1: Interrupt request at ADT input falling Fig. 42. Structure of A-D control register Data bus b7 A-D control register b0 4 P73/SRDY2/ADT/AN0 P74/AN1 P75/AN2 P76/AN3 P77/AN4 P60/AN5 P61/AN6 P62/AN7 P63/CMPIN/AN8 P64/CMPREF/AN9 P65/DAVREF/AN10 P80/DA3/AN11 P81/DA4/AN12 A-D control circuit ADT/A-D interrupt request Channel selector Comparator A-D conversion register 8 Resistor ladder AVSS ADVREF Fig. 43. Block diagram of A-D converter 43 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A Converter The 3807 group has an on-chip D-A converter with 8-bit resolution and 4 channels (DAi (i=1--4)). The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from DAi pin by setting the DAi output enable bits to "1." When using the D-A converter, the corresponding port direction register bit (P65/DAVREF/AN10, P56/DA1, P57/DA2, P80/DA3/AN11, P81/DA4/AN12) should be set to "0" (input status). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V=DAVREF x n/256 (n=0 to 255) Where DAVREF is the reference voltage. At reset, the D-A conversion registers are cleared to "0016", the DAi output enable bits are cleared to "0", and DAi pin is set to input (high impedance). The DA output is not buffered, so connect an external buffer when driving a low-impedance load. b7 b0 D-A control register (DACON : address 003316) DA1 output enable bit DA2 output enable bit DA3 output enable bit DA4 output enable bit Not used (return "0" when read) 0 : Output disabled 1 : Output enabled Fig. 44. Structure of D-A control register Data bus D-A1 conversion register (003616) D-A2 conversion register (003716) D-A3 conversion register (003816) D-A4 conversion register (003916) D-A i conversion register (8) DA i output enable bit P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12 R-2R resistor ladder Fig. 45. Block diagram of D-A converter DA i output enable bit (Note) P56/DA1 P57/DA2 P80/DA3/AN11 P81/DA4/AN12 "0" R 2R MSB R 2R R 2R R 2R R 2R R R 2R "1" 2R 2R 2R LSB D-A i conversion register (Note) AVSS P65/DAVREF/AN10 Note: i=1 to 4 "0" "1" Fig. 46. Equivalent connection circuit of D-A converter 44 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Analog Comparator An analog comparator circuit which is independent of peripheral circuits in the microcomputer is incorporated (Note). An analog comparator outputs the result of comparison with an input voltage of CMPREF pin which is specified as a reference voltage and an input voltage of CMPIN pin to CMPOUT pin. The result is "1" when the input voltage to port CMPIN is higher than the voltage applied to port CMPREF and "0" when the voltage is lower. Because the analog comparator consists of an analog MOS circuit, set the input voltage to the CMPIN pin and the CMPREF pin within the following range : VSS +1.2 V to CMPVCC-0.5V sNote The analog comparator circuit is separated from the MCU internal peripheral circuit in the microcomputer. Accordingly, even if the microcomputer runs away, the analog comparator is still in operation. For this reason, the analog comparator can be used for safety circuit design. CMPVCC P63/CMPIN /AN8 + - P64/CMPREF /AN9 CMPOUT AVSS Fig. 47. Block diagram of Analog comparator 45 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Watchdog Timer The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 8-bit watchdog timer H. qStandard operation of watchdog timer When any data is not written into the watchdog timer control register (address 001716) after resetting, the watchdog timer is in the stop state. The watchdog timer starts to count down by writing an optional value into the watchdog timer control register (address 001716) and an internal resetting takes place at an underflow of the watchdog timer H. Accordingly, programming is usually performed so that writing to the watchdog timer control register (address 001716) may be started before an underflow. When the watchdog timer control register (address 001716) is read, the values of the 6 high-order bits of the watchdog timer H, STP instruction disable bit, and watchdog timer H count source selection bit are read. (1) Initial value of watchdog timer At reset or writing to the watchdog timer control register (address 001716), each watchdog timer H and L is set to "FF16." (2) Watchdog timer H count source selection bit operation Bit 7 of the watchdog timer control register (address 001716) permits selecting a watchdog timer H count source. When this bit is set to "0", the count source becomes the underflow signal of watchdog timer L. The detection time is set then to f(XIN)=131.072 ms at 8 MHz frequency and f(XCIN)=32.768 s at 32 kHz frequency. When this bit is set to "1", the count source becomes the signal divided by 16 for f(XIN) (or f(XCIN)). The detection time in this case is set to f(XIN)=512 s at 8 MHz frequency and f(XCIN)=128 ms at 32 KHz frequency. This bit is cleared to "0" after resetting. (3) Operation of STP instruction disable bit Bit 6 of the watchdog timer control register (address 001716) permits disabling the STP instruction when the watchdog timer is in operation. When this bit is "0", the STP instruction is enabled. When this bit is "1", the STP instruction is disabled. Once the STP instruction is executed, an internal resetting takes place. When this bit is set to "1", it cannot be rewritten to "0" by program. This bit is cleared to "0" after resetting. XCIN "10" Main clock division ratio selection bits (Note) XIN "FF16" is set when watchdog timer control register is written to. "0" Watchdog timer L (8) 1/16 "00" "01" "1" Watchdog timer H (8) Data bus "FF16" is set when watchdog timer control register is written to. Watchdog timer H count source selection bit STP instruction disable bit STP instruction Reset circuit Internal reset RESET Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. Fig. 48. Block diagram of Watchdog timer b7 b0 Watchdog timer control register (WDTCON : address 001716) Watchdog timer H (for read-out of high-order 6 bit) STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer H count source selection bit 0: Watchdog timer L underflow 1: f(XIN)/16 or f(XCIN)/16 Fig. 49. Structure of Watchdog timer control register 46 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock output function The internal clock can be output from I/O port P34. Control of I/O ports and clock output function can be performed by port P2P3 control register (address 001516). b7 b0 Port P2P3 control register (P2P3C : address 001516) P34 clock output control bit 0: I/O port 1: Clock output Output clock frequency selection bits 000: 001: f(XCIN) 010: "L" fixed for output 011: "L" fixed for output 100: f(XIN) (f(XCIN) in low-speed mode) 101: f(XIN)/2 (f(XCIN)/2 in low-speed mode) 110: f(XIN)/4 (f(XCIN)/4 in low-speed mode) 111: f(XIN)/16 (f(XCIN)/16 in low-speed mode) Not used (return "0" when read) P2*P32 input level selection bit 0: CMOS level input 1: TTL level input (1) I/O ports or clock output function selection The P34 clock output control bit (b0) of port P2P3 control register selects the I/O port or clock output function. When clock output function is selected, the clock is output regardless of the port P34 direction register settings. Directly after bit 0 is written to, the port or clock output is switched synchronous to a falling edge of clock frequency selected by the output clock frequency selection bit. When memory expansion mode or microprocessor mode is selected in CPU mode register (b1, b0), clock output is selected on regardless of P34 clock output control bit settings or port P34 direction register settings. (2) Selection of output clock frequency The output clock frequency selection bits (b3, b2, b1) of port P2P3 control register select the output clock frequency. The output waveform when f(XIN) or f(XCIN) is selected, depends on XIN or XCIN input waveform however; all other output waveform settings have a duty cycle of 50%. Fig. 50. Structure of Port P2P3 control register P34 direction register P34 clock output control bit Microprocessor mode/memory expansion mode P34 port latch Output clock frequency selection bits "000" XCIN Main clock division ratio selection bits (Note) Low-speed mode "001" P34/CKOUT/o "100" High-speed or middle-speed mode 1/2 1/4 1/16 "101" "110" "111" "010" "011" XIN Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. Fig. 51. Block diagram of Clock output function 47 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Circuit ______ To reset the microcomputer, RESET pin should be held at an "L" ______ level for 2 s or more. Then the RESET pin is returned to an "H" level (the power source voltage should be between 2.7 V and 5.5 V, and the oscillation should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.54 V for VCC of 2.7 V. Poweron Power source voltage 0V Reset input voltage 0V (Note) RESET VCC 0.2VCC Note : Reset release voltage ; Vcc=2.7 V RESET VCC Power source voltage detection circuit Fig. 52. Reset circuit example XIN RESET Internal reset Address ? ? ? ? FFFC FFFD ADH,L Reset address from the vector table. Data ? ? ? ? ADL ADH SYNC XIN: 10.5 to 18.5 clock cycles Notes 1: The frequency relation of f(XIN) and f() is f(XIN)=8 * f(). 2: The question marks (?) indicate an undefined state that depends on the previous state. Fig. 53. Reset sequence 48 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Address Register contents (1) Port P0 (2) Port P0 direction register (3) Port P1 (4) Port P1 direction register (5) Port P2 (6) Port P2 direction register (7) Port P3 (8) Port P3 direction register (9) Port P4 (10) Port P4 direction register (11) Port P5 (12) Port P5 direction register (13) Port P6 (14) Port P6 direction register (15) Port P7 (16) Port P7 direction register (17) Port P8 (18) Port P8 direction register (19) Timer XY control register (20) Port P2P3 control register (21) Pull-up control register (22) Watchdog timer control register (23) Serial I/O1 status register (24) Serial I/O1 control register (25) UART control register (26) Serial I/O2 control register 1 (27) Serial I/O2 control register 2 (28) Timer X (low-order) (29) Timer X (high-order) (30) Timer Y (low-order) (31) Timer Y (high-order) (32) Timer 1 (33) Timer 2 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16 001016 001116 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 (34) Timer 3 (35) Timer X mode register (36) Timer Y mode register (37) Timer 123 mode register (38) Real time port register 0--7 (39) Real time port control register 0 (40) Real time port control register 1 R/W pointer Output pointer (41) Real time port control register 2 R/W pointer Output pointer (42) Real time port control register 3 (43) Timer A (low-order) (44) Timer A (high-order) (45) Timer B (low-order) (46) Timer B (high-order) (47) D-A control register (48) A-D control register (49) D-A1 conversion register (50) D-A2 conversion register (51) D-A3 conversion register (52) D-A4 conversion register (53) Interrupt edge selection register (54) CPU mode register (55) Interrupt request register 1 (56) Interrupt request register 2 (57) Interrupt control register 1 (58) Interrupt control register 2 (59) Processor status register (60) Program counter Address Register contents 002616 002716 002816 002916 002A16 FF16 0016 0016 0016 0016 002B16 1 0 0 1 0 0 0 0 002C16 1 111 111 002D16 1 111 111 002E16 002F16 003016 003116 003216 003316 0016 FF16 FF16 FF16 FF16 0016 0000 0000 001416 0 0 0 0 0 0 1 1 001516 * 0 0 0 0 0 0 0 001616 0016 003416 0 0 0 1 0 0 0 0 003616 003716 003816 003916 003A16 0016 0016 0016 0016 0016 001716 0 0 1 1 1 1 1 1 001916 1 0 0 0 0 0 0 0 001A16 0016 001B16 1 1 1 0 0 0 0 0 001D16 0016 003B16 0 1 0 0 1 0 * 0 003C16 003D16 003E16 003F16 0016 0016 0016 0016 001E16 0 0 0 0 0 1 1 1 002016 002116 002216 002316 002416 002516 FF16 FF16 FF16 FF16 FF16 0116 (PS) ! ! ! ! ! 1 ! ! (PCH) (PCL) FFFD16 contents FFFC16 contents * The initial values depend on level of port CNVSS. X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. Fig. 54. Internal status at reset 49 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock Generating Circuit The 3807 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No external resistor is needed between XIN and XOUT since a feed-back resistor exists on-chip. However, an external feed-back resistor is needed between XCIN and XCOUT. Immediately after poweron, only the XIN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. qFrequency control (1) Middle-speed mode The internal clock is the frequency of XIN divided by 8. After reset, this mode is selected. (2) High-speed mode The internal clock is half the frequency of XIN. (3) Low-speed mode The internal clock is half the frequency of XCIN. sNote If you switch the mode between middle/high-speed and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub clock to stabilize, especially immediately after poweron and at returning from stop mode. When switching the mode between middle/high-speed and low-speed, set the frequency on condition that f(XIN) > 3f(XCIN). (4) Low power consumption mode The low power consumption operation can be realized by stopping the main clock XIN in low-speed mode. To stop the main clock, set bit 5 of the CPU mode register to "1." When the main clock XIN is restarted (by setting the main clock stop bit to "0"), set enough time for oscillation to stabilize. By clearing furthermore the XCOUT drivability selection bit (b3) of CPU mode register to "0", low power consumption operation of less than 55 A (VCC=3 V, XCIN=32 kHz) can be realized by reducing the drivability between XCIN and XCOUT. At reset or during STP instruction execution this bit is set to "1" and a reduced drivability that has an easy oscillation start is set. The sub-clock XCIN-XCOUT oscillating circuit can not directly input clocks that are generated externally. Accordingly, make sure to cause an external resonator to oscillate. qOscillation control (1) Stop mode If the STP instruction is executed, the internal clock stops at an "H" level, and XIN and XCIN oscillators stop. Timer 1 is set to "FF16" and timer 2 is set to "0116." Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except timer 3 count source selection bit (b4) are cleared to "0". Set the timer 2/INT3 interrupt source bit to "1" and timer 1/INT2 as well as timer 2/INT3 interrupt enable bit to disabled ("0") before executing the STP instruction. Oscillator restarts when an external interrupt is received, but the internal clock is not supplied to the CPU (remains at "H") until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. The internal clock is supplied for the first time, when timer 2 underflows. Therefore make sure not to set the timer 2/INT3 interrupt request bit to "1" before the STP instruction stops the oscillator. When the ______ oscillator is restarted by reset apply "L" level to port RESET until the oscillation is stable since a wait time will not be generated. (2) Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. XCIN Rf XCOUT Rd CCOUT XIN XOUT CCIN CIN COUT Fig. 55. Ceramic resonator circuit XCIN Rf XCOUT Rd XIN XOUT open CCIN External oscillation circuit CCOUT VCC VSS Fig. 56. External clock input circuit 50 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER XCIN XCOUT "0" "1" Port XC switch bit Timer 1 count source selection bits Timer 2 count source selection bit "0" XIN XOUT Main clock division ratio selection bits (note) Low-speed mode "10" "01" Timer 1 1/2 High-speed or middle-speed mode 1/4 1/2 "00" "1" Timer 2 Main clock division ratio selection bits (note) Middle-speed mode High-speed or low-speed mode Main clock stop bit Timing (internal clock) Q S R STP instruction WIT instruction SQ R QS R STP instruction Reset Interrupt disable flag l Interrupt request Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register. When low-speed mode is selected, set port Xc switch bit (b4) to "1". Fig. 57. System clock generating circuit block diagram (Single-chip mode) 51 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Reset Middle-speed mode (f( ) =1 MHz) C M 7=0 C M 6=1 C M 5=0(8MHz oscillating) C M 4=0(32kHz stopped) CM6 "1 " High-speed mode (f( ) =4MHz) "0 " C M 7=0 C M 6=0 C M 5=0(8MHz oscillating) C M 4=0(32kHz stopped) "0 " CM " "1 6 CM " "1 4 "0 " "0 " CM4 "1 " " "0 " High-speed mode (f( ) =4MHz) Middle-speed mode (f( ) =1MHz) C M 7=0 C M 6=1 C M 5=0(8MHz oscillating) C M 4=1(32kHz oscillating) CM6 "1 " "0 " "1 " 6 "1 "0 " " CM7 "1 " Low-speed mode (f( ) =16 kHz) C M 7=1 C M 6=0 C M 5=0(8MHz oscillating) C M 4=1(32kHz oscillating) "0 " CM "0 7 CM " C M7=0 C M6=0 C M5=0(8MHz oscillating) C M4=1(32kHz oscillating) CM4 "1 " CM "0 4 " CM "1 6 "1 " "0 " b7 b4 CPU mode register (CPUM : address 003B16) CM4 : Port Xc switch bit 0 : I/O port function (stop oscillating) 1 : XCIN-XCOUT oscillating function CM5 : Main clock (XIN- XOUT) stop bit 0 : Operating 1 : Stopped CM7,CM6 : Main clock division ratio selection bit b7 b6 0 0 : = f(XIN)/2 ( High-speed mode) 0 1 : = f(XIN)/8 (Middle-speed mode) 1 0 : = f(XCIN)/2 (Low-speed mode) 1 1 : Not available C M 7=1 C M 6=0 C M 5=1(8MHz stopped) C M 4=1(32kHz oscillating) Note 1:Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow . ) 2:The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3:Timer operates in the wait mode. 4:When the stop mode is ended, a delay of approximately 1 ms occurs by Timer 1 and Timer 2 in middle/high-speen mode. 5:When the stop mode is ended, a delay of approximately 0.25 s occurs by Timer 1 and Timer 2 in low-speed mode. 6:Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/highspeed mode. 7:The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. indicates the internal clock. Fig. 58. State transitions of system clock 52 CM5 "1 " Low-speed mode (f( ) =16 kHz) "0 " MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Processor Mode Single-chip mode, memory expansion mode, and microprocessor mode can be selected by changing the contents of the processor mode bits (CM0 and CM1 : b1 and b0 of address 003B16). In memory expansion mode and microprocessor mode, memory can be expanded externally through ports P0 to P3. In these modes, ports P0 to P3 lose their I/O port functions and become bus pins. Table. 7. Port functions in memory expansion mode and microprocessor mode Port Name Function Port P0 Outputs 8-bits low-order byte of address. Port P1 Outputs 8-bits high-order byte of address. Port P2 Operates as I/O pins for data D7 to D0 (including instruction code) Port P3 P30 and P31 function only as output pins (except that the port latch cannot be read). ____ P32 is the ONW input pin. P33 is the RESTOUT output pin. (Note) P34 is the output pin. 000016 000816 SFR area 000016 000816 SFR area 004016 internal RAM reserved area 004016 internal RAM reserved area 084016 084016 YYYY16 internal ROM * P35 is the SYNC output pin. ___ ___ P36 is the WR output pin, and P37 is the RD output pin. Note : If CNVSS is connected to VSS, the microcomputer goes to single-chip mode after a reset, so this pin cannot be used as the RESETOUT output pin. (1) Single-chip mode Select this mode by resetting the microcomputer with CNVSS connected to VSS. (2) Memory expansion mode Select this mode by setting the processor mode bits (b1, b0) to "01" in software with CNVSS connected to VSS. This mode enables external memory expansion while maintaining the validity of the internal ROM. However, some I/O devices will not support the memory expansion mode. Internal ROM will take precedence over external memory if addresses conflict. (3) Microprocessor mode Select this mode by resetting the microcomputer with CNVSS connected to VCC, or by setting the processor mode bits to "10" in software with CNVSS connected to VSS. In microprocessor mode, the internal ROM is no longer valid and external memory must be used. FFFF16 Memory expansion mode FFFF16 Microprocessor mode The shaded area are external memory area. *: YYYY16 indicates the first address of internal ROM. Fig. 59. Memory maps in various processor modes b7 b0 CPU mode register (CPUM : address 003B16) Processor mode bits (CM1, CM0) b1 b0 0 0 1 1 0: Single-chip mode 1: Memory expansion mode 0: Microprocessor mode 1: Not available Stack page selection bit 0: 0 page 1: 1 page Fig. 60. Structure of CPU mode register 53 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus control at memory expansion _____ The 3807 group has a built-in ONW function to facilitate access to external (expanded) memory and I/O devices in memory expansion mode or microprocessor mode. _____ If an "L" level signal is input to port P32/ONW when the CPU is in a read or write state, the corresponding read or write cycle is___ extended ___ by one cycle of . During this extended period, the RD or WR signal remains at "L". This extension function is valid only for writing to and reading from addresses 000016 to 000716 and 084016 to FFFF16, and only read and write cycles are extended. Read cycle Dummy cycle Write cycle Read cycle Dummy cycle Write cycle AD15--AD0 RD WR ONW * * * * Period during which ONW input signal is received During this period, the ONW signal must be fixed at either "H" or "L". At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 000816 to 083F16, regardless of whether the ONW signal is received. _____ Fig. 61. ONW function timing 54 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is "1." After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(XIN) is at least on 500 kHz during an A-D _____ conversion. (When the ONW pin has been set to "L", the A-D conversion will take twice as long to match the longer bus cycle, and so f(XIN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conversion. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request register, execute at least one instruction before performing a BBC or BBS instruction. D-A Converter The accuracy of the D-A converter becomes rapidly poor under the VCC = 4.0 V or less condition; a supply voltage of VCC 4.0 V is recommended. When a D-A converter is not used, set all values of D-Ai conversion registers (i=1 to 4) to "0016." Decimal Calculations *To calculate in decimal notation, set the decimal mode flag (D) to "1", then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. *In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Instruction Execution Time The instruction execution time is obtained by multiplying the frequency of the internal clock by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock is half of the XIN frequency in high-speed mode. _____ When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock may be one fourth of the XIN frequency. Timers If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). Multiplication and Division Instructions *The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. *The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used: *The data transfer instruction (LDA, etc.) *The operation instruction when the index X mode flag (T) is "1" *The addressing mode which uses the value of a direction register as an index *The bit-test instruction (BBC or BBS, etc.) to a direction register *The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an external clock and it is to output the SRDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to "1." Serial I/O1 continues to output the final bit from the TXD pin after transmission is completed. SOUT2 pin for serial I/O2 goes to high impedance after transfer is completed. When in serial I/O1 (clock-synchronous mode) or in serial I/O2 an external clock is used as synchronous clock, write transmission data to both the transmit buffer register and serial I/O2 register, during transfer clock is "H." 55 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON USAGE Handling of Source Pins In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (Vss pin) and between power source pin (VCC pin) and analog power source input pin (AVSS pin). Besides, connect the capacitor to as close as possible. For bypass capacitor which should not be located too far from the pins to be connected, a ceramic capacitor of 0.01 F--0.1 F is recommended. P34 clock output function In the case of using an I/O port P34 as a clock output function, note the following : when an output clock frequency is changed during outputting a clock, the port may feed a noise having a shorter pulse width than the standard at the switch timing. Besides, it also may happen at the timing for switching the low-speed mode to the middle/ high-speed mode. Timer X and timer Y In the pulse period measurement mode or the pulse width measurement mode for timers X and Y, set the "L" or "H" pulse width of input signal from CNTR0/CNTR1 pin to 2 cycles or more of a timer count source. EPROM version/One Time PROM version The CNVSS pin is connected to the internal memory circuit block by a low-ohmic resistance, since it has the multiplexed function to be a programmable power source pin (VPP pin) as well. To improve the noise reduction, connect a track between CNVSS pin and VSS pin or VCC pin with 1 to 10 k resistance. The mask ROM version track of port CNVSS has no operational interference even if it is connected via a resistor. 56 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM production: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built-in EPROM version can be read or programmed with a general purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. Table. 8. Special programming adapter Package 80P6N-A 80D0 Name of Programming Adapter PCA4738F-80A PCA4738L-80A The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To ensure proper operation after programming, the procedure shown in Figure 64 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150 C exceeding 100 hours. Fig. 62. Programming and testing of One Time PROM version 57 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Table 9 Absolute maximum ratings Symbol VCC CMPVCC VI Power source voltage Analog comparator power source voltage Input voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87, ADVREF ____________ Parameter Conditions Ratings -0.3 to 7.0 -0.3 to 7.0 -0.3 to VCC +0.3 Unit V V V VI VI VI VI VID VO Input voltage Input voltage Input voltage In-phase input voltage RESET, XIN CNVSS (ROM version) CNVSS (PROM version) CMPIN, CMPREF |CMPIN-CMPREF| P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, XOUT CMPOUT All voltages are based on VSS. Output transistors are cut off. -0.3 to VCC +0.3 -0.3 to 7 -0.3 to 13 -0.3 to CMPVCC +0.3 CMPVCC -0.3 to VCC +0.3 V V V V V V Differential input voltage Output voltage VO Pd Topr Tstg Output voltage Power dissipation -0.3 to CMPVCC +0.3 Ta = 25C 500 -20 to 85 -40 to 125 V mW C C Operating temperature Storage temperature 58 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RECOMMENDED OPERATING CONDITIONS Table 10 Recommended operating conditions (1) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol VCC VSS ADVREF DAVREF CMPVCC AVSS VIA VIH Power source voltage Power source voltage A-D comparator reference voltage D-A comparator reference voltage Analog comparator power source voltage Analog power source voltage A-D comparator input voltage "H" input voltage AN0--AN12 P00--P07, P10--P17, P30, P31, P33--P37, P40--P47, P50--P57, P60--P65, P70--P77, P80--P87 P20--P27, P32 (Note) ______ Parameter f(XIN) 4.1MHz Limits Min. 2.7 4.0 2.0 2.7 VCC 0 AVSS 0.8VCC VCC VCC f(XIN) = 8MHz Typ. 5.0 5.0 0 VCC VCC Max. 5.5 5.5 Unit V V V V V V V V V VIH VIH VIH VIL "H" input voltage (CMOS input level selected) P20--P27, P32 "H" input voltage (TTL input level selected) "H" input voltage "L" input voltage RESET, XIN, CNVSS P00--P07, P10--P17, P30, P31, P33--P37, P40--P47, P50--P57, P60--P65, P70--P77, P80--P87 P20--P27, P32 (Note) ______ 0.8VCC 2.0 0.8VCC 0 VCC VCC VCC 0.2VCC V V V V VIL VIL VIL VIL "L" input voltage (CMOS input level selected) P20--P27, P32 "L" input voltage (TTL input level selected) "L" input voltage "L" input voltage RESET, CNVSS XIN 0 0 0 0 0.2VCC 0.8 0.2VCC 0.16VCC V V V V Note: When Vcc is 4.0 to 5.5 V. Table 11 Recommended operating conditions (2) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol IOH(peak) IOH(peak) IOL(peak) IOL(peak) Parameter "H" total peak output current (Note) "H" total peak output current (Note) "L" total peak output current (Note) "L" total peak output current (Note) P24-P27 "L" total peak output current (Note) "H" total average output current (Note) "H" total average output current (Note) "L" total average output current (Note) "L" total average output current (Note) P24-P27 "L" total average output current (Note) P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P23, P30-P37, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P27, P30-P37, P80-P87 P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 P00-P07, P10-P17, P20-P23, P30-P37, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77 Limits Min. Typ. Max. -80 -80 80 80 80 80 -40 -40 40 40 40 40 Unit mA mA mA mA mA mA mA mA mA mA mA mA IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Note: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100ms. The total peak current is the peak value of all the currents. 59 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 12 Recommended operating conditions (3) (Vcc = 2.7 to 5.5 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol IOH(peak) "H" peak output current (Note 1) Parameter P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 P00-P07, P10-P17, P20-P23, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 in single chip mode in memory expansion mode and microprocessor mode P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 P00-P07, P10-P17, P20-P23, P30-P37, P40-P47, P50-P57, P60-P62, P65, CMPOUT, P70-P77, P80-P87 in single chip mode in memory expansion mode and microprocessor mode High-speed mode 4.0V VCC 5.5V High-speed mode 2.7V VCC 4.0V Middle-speed mode 4.0V VCC 5.5V Middle-speed mode (Note 5) 2.7V VCC 4.0V Middle-speed mode (Note 5) 2.7V VCC 4.0V f(XCIN) Note1: 2: 3: 4: Sub-clock input oscillation frequency (Note 3, 4) 32.768 Limits Min. Typ. Max. -10 Unit mA IOL(peak) "L" peak output current (Note 1) 10 mA IOL(peak) "L" peak output current (Note 1) P24-P27 "H" average output current (Note 2) 20 10 -5 mA mA mA IOH(avg) IOL(avg) "L" average output current (Note 2) 5 mA IOL(avg) "L" average output current (Note 2) P24-P27 Main clock input oscillation frequency (Note 3) 15 5 8 3VCC-4 8 8 3VCC-4 50 mA mA MHz MHz MHz MHz MHz kHz f(XIN) The peak output current is the peak current flowing in each port. The average output current IOL (avg), IOH (avg) in an average value measured over 100ms. When the oscillation frequency has a duty cyde of 50%. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(XCIN) f(XIN)/ 3. 5: When using the timer X/Y, timer A/B (real time output port), timer 1/2/3, serial I/O1, serial I/O2, and A-D converter, set the main clock input oscillation frequency to the max. 3 Vcc-4 (MHz). 60 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER ELECTRICAL CHARACTERISTICS Table 13 Electrical characteristics (1) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol VOH Parameter "H" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, CMPOUT (Note 1) "L" output voltage P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P62, P65, P70-P77, P80-P87, CMPOUT Hysteresis Hysteresis Hysteresis "H" input current P42, P43, P51-P55, P73 (Note 2), CNTR0, CNTR1, INT0-INT4, ADT RXD, SCLK1, SIN2, SCLK2 ____________ Test conditions IOH = -10mA VCC = 4.0 to 5.5V IOH = -1.0mA VCC = 2.7 to 5.5V IOL = 10mA VCC = 4.0 to 5.5V IOL = 1.6mA VCC = 2.7 to 5.5V Limits Min. VCC-2.0 VCC-1.0 2.0 0.4 0.4 0.5 0.5 Typ. Max. Unit V V V V V V V VOL VT+-VT- VT+-VT- VT+-VT- IIH RESET P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87 ____________ VI = VCC (Pin floating. Pull-up transistors "off") VI = VCC VI = VCC VI = VSS (Pin floating. Pull-up transistors "off") VI = VSS VI = VSS Pull-up transistors "on" VI = VSS When clock stopped 2.0 -4 -0.2 4 5.0 A IIH IIH IIL "H" input current "H" input current "L" input current RESET, CNVSS XIN P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, P50-P57, P60-P65, P70-P77, P80-P87 ____________ 5.0 -5.0 A A A IIL IIL IIL VRAM "L" input current "L" input current "L" input current RAM hold voltage RESET, CNVSS XIN P00-P07, P10-P17, P20-P27 -5.0 A A mA 5.5 V Note1: P45 is measured when the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". P71, and P12 are measured when the P71/SOUT2 and P72/SCLK2 P-channel output disable bit of the serial I/O2 control register 1 (bit 7 of address 001D16). 2: P73 is measured when the AD external trigger valid bit of the A-D control register (bit 6 of address 003416) is "1". 61 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Table 14 Electrical characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol ICC Parameter Power source current Test conditions High-speed mode f(XIN) = 8MHz f(XCIN) = 32.768kHz Output transistors "off" High-speed mode f(XIN) = 8MHz (in WIT state) f(XCIN) = 32.768kHz Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode f(XIN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode (VCC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz Low-power dissipation mode (CM3 = 0) Output transistors "off" Low-speed mode (VCC = 3V) f(XIN) = stopped f(XCIN) = 32.768kHz (in WIT state) Low-power dissipation mode (CM3 = 0) Output transistors "off" Middle-speed mode f(XIN) = 8MHz f(XCIN) = stopped Output transistors "off" Middle-speed mode f(XIN) = 8MHz (in WIT state) f(XCIN) = stopped Output transistors "off" Increment when A-D conversion is executed f(XIN) = 8MHz All oscillation stopped (in STP state) Output transistors "off" CMPICC Analog comparator Power source current Ta = 25C Ta = 85C 200 Limits Min. Typ. 6.8 Max. 13 Unit mA 1.6 mA 60 200 A 20 40 A 20 55 A 5.0 10.0 A 4.0 7.0 mA 1.5 mA 800 0.1 1.0 10 500 A A A A 62 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D CONVERTER CHARACTERISTICS Table 15 A-D converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, ADVREF = 2.0 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted) Symbol -- -- tCONV RLADDER IADVREF II(AD) Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current A-D port input current ADVREF ADVREF "on" "off" Parameter Test conditions Min. Limits Typ. Max. 8 2 50 Unit Bits LSB tc() k A A A VCC = ADVREF = 5.0V 12 ADVREF = 5.0V 50 35 150 100 200 5 5.0 D-A CONVERTER CHARACTERISTICS Table 16 D-A converter characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, DAVREF = 2.7 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted) Symbol -- -- tsu Ro IDAVREF Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) 1 2.5 VCC = 4.0 to 5.5V VCC = 2.7 to 4.0V Parameter Test conditions Limits Typ. Unit Bits % % s k mA Min. Max. 8 1.0 2.5 3 4 3.2 Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being "0016". ANALOG COMPARATOR CHARACTERISTICS Table 17 Analog comparator characteristics (Vcc = 2.7 to 5.5 V, Vss = AVss = 0 V, CMPVcc = 2.7 V to Vcc, Ta = - 20 to 85 C, unless otherwise noted) Symbol VIO IB IIO VICM AV tPD Input offset voltage Input bias current Input offset current In-phase input voltage range Voltage gain Response time CMPVCC = 5.0V CMPREF = 2.5V 1.2 60 2500 ns Parameter Test conditions CMPVCC = 5.0V CMPREF = 2.5V, Rs = 0 Limits Min. Typ. 3 Max. 50 5 5 CMPVCC -0.5 Unit mV A A V 63 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS Table 18 Timing requirements (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol ____________ Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "H" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input set up time Limits Min. 2 125 50 50 200 80 80 80 80 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Serial I/O2 clock input hold time Note: When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART). Table 19 Timing requirements (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol ____________ Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width CNTR0, CNTR1 input cycle time CNTR0, CNTR1 input "H" pulse width CNTR0, CNTR1 input "L" pulse width INT0 to INT4 input "H" pulse width INT0 to INT4 input "L" pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input "H" pulse width (Note) Serial I/O1 clock input "L" pulse width (Note) Serial I/O1 clock input set up time Serial I/O1 clock input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input "H" pulse width Serial I/O2 clock input "L" pulse width Serial I/O2 clock input set up time Limits Min. 2 243 100 100 500 230 230 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tC(CNTR) tWH(CNTR) tWL(CNTR) tWH(INT) tWL(INT) tC(SCLK1) tWH(SCLK1) tWL(SCLK1) tsu(RXD-SCLK1) th(SCLK1-RXD) tC(SCLK2) tWH(SCLK2) tWL(SCLK2) tsu(SIN2-SCLK2) th(SCLK2-SIN2) Serial I/O2 clock input hold time Note: When bit 6 of address 001A16 is "1" (clock synchronous). Divide this value by four when bit 6 of address 001A16 is "0" (UART). 64 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SWITCHING CHARACTERISTICS Table 20 Switching characteristics (1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig. 3.1.1 10 10 0 30 30 30 Fig. 3.1.1 tC(SCLK2)/2-160 tC(SCLK2)/2-160 200 -30 30 30 Test conditions Fig. 3.1.1 Limits Min. tC(SCLK1)/2-30 tC(SCLK1)/2-30 140 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P71/SOUT2, P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded. Table 21 Switching characteristics (2) (Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, unless otherwise noted) Symbol tWH(SCLK1) tWL(SCLK1) td(SCLK1-TXD) tv(SCLK1-TXD) tr(SCLK1) tf(SCLK1) tWH(SCLK2) tWL(SCLK2) td(SCLK2-SOUT2) tv(SCLK2-SOUT2) tf(SCLK2) tr(CMOS) tf(CMOS) Parameter Serial I/O1 clock output "H" pulse width Serial I/O1 clock output "L" pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output "H" pulse width Serial I/O2 clock output "L" pulse width Serial I/O2 output delay time (Note 2) Serial I/O2 output valid time (Note 2) Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) Fig. 3.1.1 20 20 0 50 50 50 Fig. 3.1.1 tC(SCLK2)/2-240 tC(SCLK2)/2-240 400 -30 50 50 Test conditions Fig. 3.1.1 Limits Min. tC(SCLK1)/2-50 tC(SCLK1)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: When the P45/TXD P-channel output disable bit of the UART control register (bit 4 of address 001B16) is "0". 2: When the P71/SOUT2, P72/SCLK2 P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D16) is "0". 3: XOUT pin is excluded. 65 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE Table 22 Timing requirements in memory expansion and microprocessor mode(1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, in high-speed mode, unless otherwise noted) Symbol tsu(ONW-) th(-ONW) tsu(DB-) th(-DB) tsu(ONW-RD), tsu(ONW-WR) th(RD-ONW), th(WR-ONW) tsu(DB-RD) th(RD-DB) __ __ __ ____ __ ____ ____ __ ____ __ ____ ____ _________ Parameter ONW input set up time _________ Limits Min. -20 -20 50 0 -20 -20 50 0 Typ. Max. Unit ns ns ns ns ns ns ns ns ONW input hold time Data bus set up time Data bus hold time ________ ONW input set up time _________ ONW input hold time Data bus set up time Data bus hold time SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE Table 23 Switching characteristics in memory expansion and microprocessor mode(1) (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = - 20 to 85 C, in high-speed mode, unless otherwise noted) Symbol tc() tWH() tWL() td(-AH) td(-AL) tv(-AH) tv(-AL) td(-SYNC) tv(-SYNC) td(-DB) tv(-DB) tWL(RD), tWL(WR) __ __ Parameter Test conditions Fig. 3.1.1 Limits Min. tC(XIN)-10 tC(XIN)-10 16 20 2 2 5 5 16 5 15 10 tC(XIN)-10 3tC(XIN)-10 tC(XIN)-35 tC(XIN)-40 2 2 tC(XIN)-16 tC(XIN)-20 5 5 15 10 200 0 100 30 30 35 40 Typ. 2tC(XIN) Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns clock cycle time clock "H" pulse width clock "L" pulse width AD15-AD8 delay time AD7-AD0 delay time AD15-AD8 valid time AD7-AD0 valid time SYNC delay time SYNC valid time Data bus delay time Data bus valid time __ __ ___ ___ RD pulse width, WR pulse width RD pulse width, WR pulse width (When one-wait is valid) td(AH-RD), td(AH-WR) td(AL-RD), td(AL-WR) tv(RD-AH), tv(WR-AH) tv(RD-AL), tv(WR-AL) td(WR-DB) tv(WR-DB) td(RESET-RESETOUT) tv(-RESETOUT) ____________ _____ ____________ __ __ __ __ __ __ __ __ __ __ AD15-AD8 delay time AD7-AD0 delay time AD15-AD8 valid time AD7-AD0 valid time Data bus delay time Data bus valid time _______________ RESETOUT output delay time _______________ RESETOUT output valid time (Note) Note: ____________ The RESETOUT output goes "H" in sync with the fall of the clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes "H". 66 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Measurement output pin 100pF Measurement output pin 1k 100pF CMOS output N-channel open-drain output Fig. 63 Circuit for measuring output switching characteristics(1) Fig. 64 Circuit for measuring output switching characteristics (2) 67 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Diagram tC(CNTR) tWH(CNTR) tWL(CNTR) 0.2VCC CNTR0, CNTR1 0.8VCC tWH(INT) tWL(INT) 0.2VCC INT0 INT4 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tC(SCLK1), tC(SCLK2) tr tWL(SCLK1), tWL(SCLK2) 0.2VCC tsu(RXD-SCLK1), tsu(SIN2-SCLK2) 0.8VCC tWH(SCLK1), tWH(SCLK2) SCLK1 SCLK2 th(SCLK1-RXD), th(SCLK2-SIN2) RXD SIN2 0.8VCC 0.2VCC td(SCLK1-TXD),td(SCLK2-SOUT2) tv(SCLK1-TXD), tv(SCLK2-SOUT2) TXD SOUT2 Fig. 65 Timing diagram (1) (in single-chip mode) 68 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Diagram in Memory Expansion Mode and Microprocessor Mode (CMOS level input) tC( tWH( 0.5VCC td( - AH) ) ) tWL( ) tv( 0.5VCC - AH) AD15 AD8 td( - AL) tv( 0.5VCC - AL) AD7 AD0 td( - SYNC) tv( - SYNC) SYNC 0.5VCC td( - WR) tv( - WR) RD,WR tSU(ONW ) 0.5VCC th( - ONW ) ONW 0.8VCC 0.2VCC tSU(DB) th( - DB) DB0 DB7 (At CPU reading) DB0 DB7 (At CPU writing) 0.8VCC 0.2VCC td( -DB) tv( 0.5VCC -DB) Timing Diagram in Microprocessor Mode RESET 0.8VCC 0.2VCC 0.5VCC td(RESET- RESETOUT) tv( - RESETOUT) RESETOUT 0.5VCC Fig. 66 Timing diagram (2) (in memory expansion mode and microprocessor mode) 69 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Diagram in Memory Expansion Mode and Microprocessor Mode (CMOS level input) tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 0.5VCC tv(RD-AH) tv(WR-AH) AD15 AD8 0.5VCC td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AD7 AD0 0.5VCC tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW) th(WR-ONW) ONW (At CPU reading) RD 0.8VCC 0.2VCC 0.5VCC tSU(DB-RD) th(RD-DB) DB0 DB7 0.8VCC 0.2VCC (At CPU writing) WR td(WR-DB) 0.5VCC tv(WR-DB) 0.5VCC DB 0 DB7 Fig. 67 Timing diagram (3) (in memory expansion mode and microprocessor mode) 70 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Diagram in Memory Expansion Mode and Microprocessor Mode (TTL level input) tC( tWH( 2.0V 0.8V ) ) tWL( ) td( - AH) tv( 2.0V 0.8V - AH) AD15 AD8 td( - AL) tv( 2.0V 0.8V - AL) AD7 AD0 td( - SYNC) tv( - SYNC) SYNC 2.0V 0.8V td( - WR) tv( - WR) RD,WR tSU(ONW ) 2.0V 0.8V th( - ONW ) ONW 2.4V 0.45V tSU(DB- ) th( - DB) DB0 DB7 (At CPU reading) DB0 DB7 (At CPU writing) 2.4V 0.45V td( - DB) tv( 2.0V 0.8V - DB) Timing Diagram in Microprocessor Mode RESET 0.8VCC 0.2VCC 2.0V 0.8V td(RESET- RESETOUT) tv( - RESETOUT) RESETOUT 2.0V 0.8V Fig. 68 Timing diagram (4) (in memory expansion mode and microprocessor mode) 71 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timing Diagram in Memory Expansion Mode and Microprocessor Mode (TTL level input) tWL(RD) tWL(WR) RD,WR td(AH-RD) td(AH-WR) 2.0V 0.8V tv(RD-AH) tv(WR-AH) AD15 AD8 2.0V 0.8V td(AL-RD) td(AL-WR) tv(RD-AL) tv(WR-AL) AD7 AD0 2.0V 0.8V tsu(ONW-RD) tsu(ONW-WR) th(RD-ONW ) th(WR-ONW ) ONW 2.4V 0.45V (At CPU reading) RD 2.0V 0.8V tSU(DB-RD) th(RD-DB) DB0 DB7 2.4V 0.45V (At CPU writing) WR 2.0V 0.8V td(WR-DB) tv(WR-DB) 2.0V 0.8V DB0 DB7 Fig. 69 Timing diagram (5) (in memory expansion mode and microprocessor mode) 72 MITSUBISHI MICROCOMPUTERS 3807 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Keep safety first in your circuit designs! * Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials * * * These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. * * * * (c) 1996 MITSUBISHI ELECTRIC CORP. H-DF047-A KI-9609 New publication, effective Sep. 1996. Specifications subject to change without notice. REVISION DESCRIPTION LIST Rev. No. 1.0 First Edition 3807 GROUP DATA SHEET Revision Description Rev. date 9711.30 (1/1) |
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